adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 18

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
Table 14. Clock Periods
1
Figure 5
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2126x SHARC Processor
Peripherals Reference and Managing the Core PLL on Third-
Generation SHARC Processors (EE-290).
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
Timing
Requirements
t
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CK
CCLK
MCLK
SCLK
SPICLK
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)
SCLK = serial port clock
SPICLK = SPI clock
shows core to CLKIN relationships with external oscil­
RESET
XTAL
Description
CLKIN Clock Period
(Processor) Core Clock Period
Internal memory clock = 1/2 t
Serial Port Clock Period = (t
SPI Clock Period = (t
BUF
CLKIN
4096 CLKIN
DELAY OF
CYCLES
1
DIVIDER
PMCTL
CLKIN
CCLK
PLLI
CLK
Figure 5. Core Clock and System Clock Relationship to CLKIN
RESETOUT
) × SPIR
CCLK
CCLK
) × SR
Rev. E | Page 18 of 48 | July 2008
CLKOUT
CLK_CFGx/PMCTL
FILTER
LOOP
MULTIPLIER
PLL
PLL
VCO
See
reference levels.
Note that in the user application, the PLL multiplier value
should be selected in such a way that the VCO frequency never
exceeds f
lated as follows:
where:
f
PLLM is the multiplier value programmed.
f
f
f
Timing requirements apply to signals that are controlled by cir­
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char­
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
VCO
INPUT
INPUT
INPUT
Figure 30 on Page 39
f
is the VCO frequency.
VCO
is the input frequency to the PLL.
= CLKIN when the input divider is disabled and
= CLKIN ÷ 2 when the input divider is enabled.
DIVIDER
VCO
= 2 × PLLM × f
PLL
specified in
CLK_CFGx/
PMCTL
PMCTL
INPUT
Table
under Test Conditions for voltage
16. The VCO frequency is calcu­
DIVIDE
BY 2
BUF
MCLK
RESETOUT
CCLK
CLKOUT
CORERST