admc200 Analog Devices, Inc., admc200 Datasheet
admc200
Related parts for admc200
admc200 Summary of contents
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... PLCC Package Single Power Supply Industrial Temperature Range GENERAL DESCRIPTION The ADMC200 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (DSP). It provides the functionality that is required to implement a digital control system typical application, the DSP or micro- ...
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... Measurements made with external reference. 2 Tested with PWM Switching Frequency of 25 kHz. Specifications subject to change without notice 5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock = DD 12.5 MHz – +85 C unless otherwise noted) A ADMC200AP Units 1 11 Bits ± 2 LSB max ± 2 LSB max ± 5 LSB max 4 LSB max ± ...
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... NOTE 1 All WRITES to the ADMC200 must occur within 1 system clock cycle (0 wait states). Number Symbol 25 t rdb_data dly 26 t rdb_data CLK Figure 1. Clock Input Timing CLK 24 RESET Figure 2. Reset Input Timing REV ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... PWMSYNC STOP 47 DGND –5– ADMC200 Type Description GND Digital Ground GND Digital Ground GND Digital Ground SUP +5 V Digital Power Supply No Connect GND Digital Ground I/P PWM Timer Output Disable O/P PWM Synchronization Output O/P PWM Timer Output C ...
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... Sample and Hold After powering up the ADMC200, bring the RESET pin low for a minimum of two clock cycles in order to enable A/D conver- sions. Before initiating the first conversion (CONVST) after a ) reset, the SHA time of 20 system clock cycles must occur ...
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... the stator reference frame. These are then scaled by the processor and written to the ADMC200’s PWM registers in order to drive the inverter. The figures below illustrate the Clarke and Park Trans- formations respectively 120° ...
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... Equivalent Three-Phase Stator Two-Phase Voltage Figure 10. Forward Clarke Transformation Operating/Using the Vector Transformation Block After powering up the ADMC200, RESET must be driven low for a minimum of two clock cycles to enable vector transformations. The vector transformation block can perform either a forward or reverse transformation. Reverse Transformation is defined by the following operations: ...
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... ADMC200 V (32) and both AGND pins (27, 28) should be star point con- nected at a point close to the AGND pins of the ADMC200. The DGND pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should also be connected to AGND pins close to the ADMC200. Power supplies should be decoupled at the power pins using a 0.1 µ ...
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... MHz TMS320C25-50 will derive a 12.5 MHz CLKOUT1 for CS use by the ADMC200. IRQ ADMC200 Note: A pull-up resistor is required on the IRQ (Pin 18) output RD from the ADMC200. The STOP (Pin 47) must be tied low if WR not in use. CLK D0–D11* SYSTEM CLOCK FREQUENCY The nominal range of the input clock for the ADMC200 is 6 ...
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... Park Interrupt Enable. This bit allows interrupts to be generated when the Park rotation is completed. Bit 7 ADC Interrupt Enable. This bit allows interrupts to be generated via the IRQ pin when the analog-to- digital conversion process is complete –11– ADMC200 )/Forward Result Cos +0° DS )/Forward Cos +120° QS RESET Default 0 0 ...
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... Transformation completion interrupts have been enabled. Bit 4 This bit is set to 1 when the rotation results are valid. Bit 11 If any interrupt source on the ADMC200 occurs, then this bit is set to 1. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 68-Lead Plastic Leaded Chip Carrier (PLCC) (P-68A) 0 ...