ep20k1000e Altera Corporation, ep20k1000e Datasheet - Page 76

• Manufacturer Part Number: ep20k1000e
• Description: Programmable Logic Device Family
• Manufacturer: Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet
Note to
(1)
76
t
t
t
t
t
t
t
t
t
t
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
INSUBIDIRPLL
INHBIDIRPLL
OUTCOBIDIRPLL
XZBIDIRPLL
ZXBIDIRPLL
Table 39. APEX 20KE External Bidirectional Timing Parameters
These timing parameters are sample-tested only.
Symbol
Tables 38
and 39:
Setup time for bidirectional pins with global clock at LAB adjacent Input
Register
Hold time for bidirectional pins with global clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with global clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay
Synchronous Output Enable Register output buffer enable delay
Setup time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Hold time for bidirectional pins with PLL clock at LAB adjacent Input
Register
Clock-to-output delay for bidirectional pins with PLL clock at IOE output
register
Synchronous Output Enable Register to output buffer disable delay with
PLL
Synchronous Output Enable Register output buffer enable delay with PLL
Parameter
Note (1)
Altera Corporation
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
C1 = 10 pF
Conditions