ade7566 Analog Devices, Inc., ade7566 Datasheet - Page 28

• Manufacturer Part Number: ade7566
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

ADE7566/ADE7569
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when the source of V
indicating battery switchover. Setting the EBSO bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt (see Table 20).
The ADE7566/ADE7569 can also be configured to generate an
interrupt when the source of V
indicating that the V
the EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
The flags in the IPSME SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing a 0 to these bits. Bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the
source of V
cleared when V
V
The ADE7566/ADE7569 can be configured to generate a PSM
interrupt when V
urable threshold. This threshold is set in the Temperature and
Supply Delta SFR (DIFFPROG, 0xF3), which is described in
Table 48. See the External Voltage Measurement section for
more information. Setting the EVDCIN bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables
this event to generate a PSM interrupt.
The V
measurements take place in the background at intervals to check
the change in V
the Start ADC Measurement SFR (ADCGO, 0xD8) described in
Table 49. The FVDCIN flag indicates when a V
is ready. See the External Voltage Measurement section for
details on how V
DCIN
ADC PSM Interrupt
DCIN
voltage is measured using a dedicated ADC. These
SW
. The bit is set when V
DCIN
SW
DCIN
DCIN
is connected to V
. Conversions can also be initiated by writing to
DD
changes magnitude by more than a config-
is measured.
power supply has been restored. Setting
SW
SW
changes from V
changes from V
BAT
SW
.
is connected to V
DCIN
DD
BAT
measurement
to V
to V
DD
BAT
DD
and
,
,
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V
The V
measurements take place in the background at intervals to
check the change in V
level is lower than the threshold set in the Battery Detection
Threshold SFR (BATVTH, 0xFA) or when a new measurement
is ready in the Battery ADC Value SFR (BATADC, 0xDF). See
the Battery Measurement section for more information. Setting
the EBAT bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC) enables this event to generate a PSM interrupt.
V
The V
bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set
when the V
EVDCIN bit in the IPSME SFR enables this event to generate a
PSM interrupt. This event, which is associated with the SAG
monitoring, can be used to detect a power supply (V
compromised and to trigger further actions prior to deciding a
switch of V
SAG Monitor PSM Interrupt
The ADE7566/ADE7569 energy measurement DSP monitors
the ac voltage input at the V
register is used to set the threshold for a line voltage SAG event.
The FSAG bit in the Power Management Interrupt Flag SFR
(IPSMF, 0xF8) is set if the line voltage stays below the level set
in the SAGLVL register for the number of line cycles set in the
SAGCYC register. See the Line Voltage SAG Detection section
for more information. Setting the ESAG bit in the Power
Management Interrupt Enable SFR (IPSME, 0xEC) enables this
event to generate a PSM interrupt.
BAT
DCIN
Monitor PSM Interrupt
Monitor PSM Interrupt
BAT
DCIN
voltage is measured using a dedicated ADC. These
voltage is monitored by a comparator. The FVDCIN
DD
DCIN
to V
input level is lower than 1.2 V. Setting the
BAT
.
BAT
. The FBAT bit is set when the battery
P
and V
N
input pins. The SAGLVL
DD
) being