sta2065 STMicroelectronics, sta2065 Datasheet

no-image

sta2065

Manufacturer Part Number
sta2065
Description
Cartesio? Family Infotainment Application Processor With Embedded Gps
Manufacturer
STMicroelectronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
sta2065######
Manufacturer:
ST
0
Part Number:
sta2065A2
Manufacturer:
ST
0
Part Number:
sta2065ESBA-G
Manufacturer:
ST
0
Part Number:
sta2065N
Manufacturer:
STM
Quantity:
1 512
Part Number:
sta2065N
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
sta2065N
Manufacturer:
ST
Quantity:
20 000
Part Number:
sta2065N2
Manufacturer:
ST
0
Part Number:
sta2065P2
Manufacturer:
ST
Quantity:
20 000
Features
July 2009
For further information contact your local STMicroelectronics sales office.
ARM1176 533/624 MHz host processor
– Cache: 32 KB instruction, 32 KB data
– Vector floating point unit
High performance embedded GPS subsystem
– Parallel acquisition engines for 8 GPS
– 32 tracking channels for all satellites in view
– 5 correlators per channel for urban canyon
– Multibit signal processing hardware
Advanced power management
– Separated power islands for ultra low
– Dynamic core frequency scaling
– 512-Byte embedded SRAM for back-up
System infrastructure
– LP DDR/DDR2 controller: 16/32bit data
– Static memory controller (bootable):
– One bank of 32 KB embedded SRAM
– 64-channel vector interrupt controller (VIC)
– 2 DMA controllers, 16 physical channels
– 32 DMA request for each controller
– Two external DMA requests are supported
Display and graphics
– Color LCD controller for STN,TFT or HR-
– Integrated touch screen controller and ADC
– 3D advanced graphics acceleration
– Video input port (VIP) interface
– JPEG baseline profile decoder
High throuput interfaces
– 2 ports USB 2.0 OTG with integrated
– 3 SD/MMC up to 8 bit data, 2 bootable
satellites or 4 Galileo satellites
robustness
power mode
512 MB addressable. (333 MHz DDR2,
200 MHz LPDDR)
NAND/NOR, SRAM
TFT panels with 24-bit parallel RGB
interface
physical layers
infotainment application processor with embedded GPS
Doc ID16050 Rev 1
Table 1.
Order code
STA2065N
STA2065P
STA2065A
Audio interfaces and features
– Four multichannel serial ports (I2S/TDM)
– SPDIF input interface
– C3 hardware reed-solomon decoder
– Sample rate converter
Standard interfaces
– Four 16-bit input capture/output compare
– Pulse width light modulator (PWL)
– Four autobaud UART
– Three I
– Two synchronous serial port (SSP, SPI)
– Smartcard interface
– Five 32-bit GPIO ports
Two controller area network (CAN) in
automotive version
Programmable voltage IOs: 1.8 V, 2.5 V, 3.3 V
V
TFBGA 372+100 0.65 mm pitch package,
packing in tray
Ambient temperature range: -40 / +85 °C
IOON
: 1.8 ±10%V, V
TFBGA372+100 (16x16x1.2mm)
Device summary
2
Qualification
C multimaster/slave interfaces
Automotive
Consumer
Consumer
grade
Cartesio™ family
DDON
CPU freq.
533 MHz
624 MHz
533 MHz
: V
STA2065
DD
, 1.0 ±10%V
www.st.com
Data brief
CAN
No
No
2x
1/20
20

Related parts for sta2065

sta2065 Summary of contents

Page 1

... Ambient temperature range: -40 / +85 °C Table 1. Device summary Qualification Order code grade STA2065N Consumer STA2065P Consumer STA2065A Automotive Doc ID16050 Rev 1 STA2065 Cartesio™ family Data brief : V , 1.0 ±10%V DDON DD CPU freq. CAN 533 MHz No 624 MHz No 533 MHz 2x 1/20 www ...

Page 2

... Enhanced function timer (EFT Watchdog timer (WDT Flexible static memory controller (FSMC SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DDR-SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Smartcard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample rate converter (SaRaC JPEG decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Smart graphics accelerator (SGA Color LCD controller (CLCD USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Doc ID16050 Rev 1 STA2065 ...

Page 3

... STA2065 2.6.5 2.6.6 2.6.7 2.6.8 2.7 Specific functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7.1 2.7.2 2.7.3 2.7.4 3 System features introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Power region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Frequency region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Frequency and power range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 Power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 System wakeup and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 IO groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Touchscreen controller/ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Multisupply IO ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Driving strength and slew rate programmability ...

Page 4

... STA2065 is a highly integrated SOC application processor combining host capability with high performance embedded GPS. STA2065 targets vehicle head units and mobile navigation (PND), telematics, infotainment, advanced audio and connectivity systems. The STA2065 provides all the elements that are essential to build a cost effective solution. Figure 1. ...

Page 5

... Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from these peripherals can be serviced immediately by the DMA Controller without CPU interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported. STA2065 features two DMA engines. Each DMA supports up to 8-channels and requests. 2.3.4 ...

Page 6

... Enhanced function timer (EFT) STA2065 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running counter with 7-bit prescaler two input capture/output compare functions, a pulse counter function, and a PWM channel with selectable frequency. 2.3.10 Watchdog timer (WDT) This OS resource is used to trigger a system reset in the event of software failure ...

Page 7

... STA2065 2.4.2 SD/MMC STA2065 features three SD/SDIO/MMC interfaces MHz / 8-bit. The main clock available to the peripherals is: ● PLL2CLK/13 (when PLL2CLK is 624 MHz and SRC_MMC52 = 0, 48 MHz will be generated) ● PLL2CLK/12 (when PLL2CLK is 624 MHz and SRC_MMC = 1, 52 MHz will be generated) ● ...

Page 8

... JPEG compressed thumbnails are also supported. 2.5.4 Video input STA2065 has a Video Input Port. The VIP allows to grab images from external devices, supporting parallel CCIR-656 interface MHz. This block can be used in camera mode with an imaging co-processor or a CVBS video decoder to store pixel information into system memory. It can be also used in raw mode to directly store raw data from external sensor ...

Page 9

... The multichannel serial port (MSP synchronous receive and transmit serial interface. STA2065 features four MSPs. 2.6.5 SSP STA2065 features two SSPs up to 24Mbit/sec for synchronous serial communication with external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with programmable word length bits. 2.6.6 ...

Page 10

... CODECs. External interface supports one external AC97 CODEC with 6 output (3 of them can be Double Rate Audio) and 3 input channels. 2.6.8 CAN STA2065 features two CAN modules that are compliant with the CAN specification V2.0 part B (active). The bit rate can be programmed MBaud. 2.7 Specific functions 2 ...

Page 11

... D: FSMC ● E: MMC1 (GPIO40-47, GPIO76-82), CAN0 The default voltage applied to each ring will be at reset time will be: ● A: 1.8V ● B: 1.8V ● C: 1.8V ● D: 1.8V ● E: 3.3V The “Always ON” ring remains separated as in the current STA2065 and supplied by V Doc ID16050 Rev 1 System description . IOON 11/20 ...

Page 12

... Fast) (default Fast slew rate) (Nominal, Fast) (default Fast slew rate) (200, 266, 333 MHz) (default 200 MHz) (Nominal, Fast) (default Fast slew rate) (Nominal, Fast) (default Nominal slew rate) (Nominal, Fast) (default Nominal slew rate) Doc ID16050 Rev 1 STA2065 ...

Page 13

... STA2065 3 System features introduction In this chapter, an introduction to the main STA2065 system features is given. These will be explained in detail later in this document. 3.1 Power region partition STA2065 is a device targeted to wide range of applications, starting from handheld battery powered devices thanks to an optimzed power management but also addressing in dash automotive power requirements thanks to its flexibile multivoltage IO ...

Page 14

... VCO of PLL1 or PLL2 (asynchronous configuration). STA2065 embeds a complete GPS subsystem where both gate logic and dedicated DSP work together. There are specific constraints in this subsystem in terms of minimum frequency in order to guarantee the target GPS specifications. ...

Page 15

... A dedicated FSM manages the power state transitions among NORMAL, SLOW, DOZE AND SLEEP. All other states mentioned above are SW variants of the ones managed by the FSM. Table 3 shows the summary of the power states supported by STA2065. Table 3. Power mode states Power State 32 kHz ...

Page 16

... The main power switch works in a way that puts the device either in Backup or in DEEP-SLEEP mode. In this state, the only blocks within STA2065 that are powered are the RTC, PMU, PWL, SRC and the backup RAM; at system level, only the V ...

Page 17

... STA2065 3.6 IO groups V is split into the following groups: ddio (a) ● V ddio_on ● V (This is split into 5 types: V ddiox ● V (USB 2.0 PHY transceiver) USB The IO supply type and corresponding pads details are as follows: ● Power Supply pins for the IO buffers of the always ON section. It supplies ...

Page 18

... Doc ID16050 Rev 1 OUTLINE AND MECHANICAL DATA Body 1.2mm, pitch 0.65mm TFBGA372+100 Thin profile Fine Pitch Ball Grid Array 8178590 B STA2065 ® ...

Page 19

... STA2065 5 Revision history Table 4. Document revision history Date 23-Jul-2009 Revision 1 Initial release. Doc ID16050 Rev 1 Revision history Changes 19/20 ...

Page 20

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 20/20 Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com Doc ID16050 Rev 1 STA2065 ...

Related keywords