mpc82x52a Megawin Technology, mpc82x52a Datasheet - Page 48

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mpc82x52a

Manufacturer Part Number
mpc82x52a
Description
8-bit Micro-controller
Manufacturer
Megawin Technology
Datasheet
48
SPI-MODE-3. Many device declares that they meet SPI mechanism, but few of them are
adaptive to all four modes. The MPC82x52A is flexible enough to be configured to
communicate to another device with MODE-0, MODE-1, MODE-2 or MODE-3 SPI, and play
part of Master and Slave.
There is a SFR named SPICTL designed to configure the SPI behavior of the device.
SFR: SPICTL (SPI Control register)
SSIG: = used to determine if Ignore the pin SS
SPEN: = Enable the SPI
DORD: = Data Order
MSTR: = Set to Master mode
CPOL: = Clock Polarity
CPHA: = Clock Phase
{SPR1, SPR0} := SPI clock Rate selector
SSIG
Bit-7
0:= (default)
1:=
0:= (default)
1:=
0:= (default)
1:=
0:= (default)
1:=
0:= (default)
1:=
0:= (default)
1:=
Reserve the function of pin SS
Ignore the SS pin function
Disable the SPI function. All related pins play as general-purposed I/O ports.
Enable the SPI function.
Transmit/Receive the MSB of the data byte first.
Transmit/Receive the LSB of the data byte first.
Set the SPI to play as Slave part.
Set the SPI to play as Master part.
Set the SPICLK as LOW while the communication is kept idle. That implies the leading
edge of the clock is the rising edge, and the trailing edge is the falling edge.
Set the SPICLK as HIGH while the communication is kept idle. That implies the leading
edge of the clock is the falling edge, and the trailing edge is the falling rising edge.
Data is driven when pin SS is low and changes on the trailing edge of SPICLK,
and is sampled on the leading edge. (This setting is only valid while SSIG==0.)
Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.
{0,0} := (default)
{0,1} :=
{1,0} :=
SPEN
Bit-6
Set the clock rate of the SPI as the frequency of the clock source over 16.
Set the clock rate of the SPI as the frequency of the clock source over 4.
DORD
Bit-5
MPC82x52A Data Sheet
MSTR
Bit-4
CPOL
Bit-3
CPHA
Bit-2
SPR1
Bit-1
MEGAWIN
SPR0
Bit-0

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