adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 24

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
CLOCKING AND SAMPLING RATES
CORE CLOCK
Clocks for the converters, the serial ports, and the DSP are
derived from the core clock. The core clock can be derived
directly from MCLK or it can be generated by the PLL. The
CLKSRC bit (Bit 3 in Register R0, Address 0x4000) determines
the clock source.
The INFREQ[1:0] bits should be set according to the expected
input clock rate selected by CLKSRC; this value also determines
the core clock rate and the base sampling frequency, f
For example, if the input to CLKSRC = 49.152 MHz (from
PLL), then
The PLL output clock rate is always 1024 × f
control register automatically sets the INFREQ[1:0] bits to
1024 × f
INFREQ[1:0] frequency should be set according to the MCLK
pin clock rate and the desired base sampling frequency.
INFREQ[1:0] = 1024 × f
f
S
= 49.152 MHz/1024 = 48 kHz
S
when using the PLL. When using a direct clock, the
MCLK
R1: PLL CONTROL REGISTER
÷ X
S
× (R + N/M)
S
, and the clock
CLKSRC
CONTROL REGISTER
S
.
R0: CLOCK
Figure 30. Clock Tree Diagram
768 ×
256 ×
INFREQ[1:0]
Rev. 0 | Page 24 of 88
f
f
S
S
, 1024 ×
, 512 ×
f
S
f
S
,
CLOCK
To utilize the maximum amount of DSP instructions, the core
clock should run at a rate of 1024 × f
Table 11. Clock Control Register (Register R0, Address 0x4000)
Bits
3
[2:1]
0
CORE
Bit Name
CLKSRC
INFREQ[1:0]
COREN
R57: DSP SAMPLING
f
f
f
S
S
S
R64: SERIAL PORT
R17: CONVERTER
/0.5, 1, 1.5, 2, 3, 4, 6
/0.5, 1, 1.5, 2, 3, 4, 6
/0.5, 1, 1.5, 2, 3, 4, 6
SAMPLING RATE
SAMPLING RATE
RATE SETTING
CONVSR[2:0]
DSPSR[3:0]
SPSR[2:0]
ADC_SDATA/GPIO1
DAC_SDATA/GPIO0
LRCLK/GPIO3
BCLK/GPIO2
Settings
0: Direct from MCLK pin (default)
1: PLL clock
00: 256 × f
01: 512 × f
10: 768 × f
11: 1024 × f
0: Core clock disabled (default)
1: Core clock enabled
ADCs
OUTPUT PORT
S
S
S
DATA INPUT/
S
(default)
S
.
SERIAL
DACs