w681308 Winbond Electronics Corp America, w681308 Datasheet - Page 49

• Manufacturer Part Number: w681308
• Description: Usb Audio Controller
• Manufacturer: Winbond Electronics Corp America

15.
15.1
Nuvoton 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S
master use only, and governed by the MCU. The W2S is used to both read/write EEPROM and to control various device
in
M
fo
controller supports 3 types of page writing, 8, 16 and 32 bytes. The W2S controller is designed to support maximum of 32
bytes per page. The FIFO depth can support 3 header bytes (one device ID, two address) and 32 bytes data. It has various
bus speed configurations to support wide range of EEPROM bus speed.
16.
16.1
The W681308 MCU on-chip debugger function follows the JTAG standard. It provides 8 sets of breakpoints. There is no
watchpoint. There are five JTAG-style scan chains within the 8051 and peripheral logic, which enable embedded ICE logic.
The 5 JTAG interface pins TCK (JTAG test clock input), TMS
(JTAG test data output) and nTR
pins are multiplexed with other fun
16.2
There are five JTAG-style scan chains within the TB51 core and peripheral logic interface. These enable debugging
o
power-on reset will trigg
16.3
Table 11 JTAG Pin Description
peration and configuration of Embedded-ICE logic. An external pull lo
cluded I2C interface. The W2S controller is equipped with 35 bytes FIFO
CU can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format);
r reading, just set read enable, for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S
Pin Name
nTRST
TMS
TDO
TCK
TDI
Nuvoton 2-Wire Serial Bus
Overview
ICE Function By JTAG STD. IEEE 1149.1
Overview
Scan Chains and JTAG Interface
Pin Description
er TAP controller reset once.
Type
OUT
IN
IN
IN
IN
ST (JTAG TAG controller reset) are needed to enable the operation. The JTAG interface
ction pins.
JTAG Test Data Input with internal pull-up. TDI is latched on a rising edge of TCK.
JTAG Test clock with internal pull-up.
JTAG Test-Mode Select with internal pull-up.
JTAG Test Data Output. Data is shifted out on TDO at the rising edge of TCK. TDO
output is a tri-state driver with internal weakly pull-low resister.
JTAG TAP controller reset input with internal pull-up.
XXXX PRODUCT DESCRIPTION
49
(JT
AG test mode select), TDI (JTAG test data input), TDO
w signal on nTRST will reset TAP controller or MCU
Function
performing formatting and de-formatting. The
W681308
Rev1.2