w682510 Winbond Electronics Corp America, w682510 Datasheet - Page 10

• Manufacturer Part Number: w682510
• Description: Voice Codec
• Manufacturer: Winbond Electronics Corp America

be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding
law and output coding format recommendation.
+ Full Scale
+ Zero
- Zero
- Full Scale
The PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is
sent from PCMT2 in a sequential order, synchronized with the rising edge of the BCLK signal. The
MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance
state during power-saving state or power-down. When the serial operation is selected, this pin is left
open. A pull-up resistor must be connected to this pin , as it is an open drain output. This device is
compatible with the ITU-T coding law and output coding format recommendation.
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO.
RO1 and RO2 are the receive analog outputs for channel 1 and channel 2. The output signal of the
W682510 has an amplitude of 3.46 Vpp (2.03 Vpp for W682310) around the signal ground voltage
(V
of 600 Ohms or more at 5 V supply voltage for the W682510 and 1200 Ohms at 3V supply for the
W682310. During power saving mode, these outputs are at the voltage level of V
impedance. These outputs have a feature that reduces audio “pop” noises when switching between
active and inactive states and back.
REF
7.2. R
). When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load
Level
7.1.3. PCMT2
7.2.1. RO1, RO2
ECEIVE
P
ATH
TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE
Sign bit
1
1
0
0
Chord bits
μ-Law
000
111
111
000
- 10 -
Step bits
0000
1111
1111
0000
Sign Bit
1
1
0
0
W682510/W682310
Chord Bits
A-Law
010
101
101
010
REF
with a high
Step Bits
1010
0101
0101
1010