enc28j60 Microchip Technology Inc., enc28j60 Datasheet - Page 92

• Manufacturer Part Number: enc28j60
• Description: Stand-alone Ethernet Controller With Spi Interface
• Manufacturer: Microchip Technology Inc.

ENC28J60
Packet Format..................................................................... 31
Pattern Match Filter............................................................. 51
Per Packet Control Byte Format ......................................... 39
PHID Registers ................................................................... 22
PHSTAT Registers.............................................................. 22
PHY Register Summary ...................................................... 20
PHY Registers..................................................................... 19
Pinout Diagrams.................................................................... 1
Pinout I/O Descriptions ......................................................... 4
Power-Down........................................................................ 73
Power-on Reset (POR) ....................................................... 60
R
Read Control Register (RCR) ............................................. 27
Reader Response ............................................................... 92
Reading and Writing to the Buffer ....................................... 17
Receive Buffer..................................................................... 17
Receive Filters .................................................................... 47
Receive Only Reset ............................................................ 60
Receiving Packets............................................................... 43
Registers
DS39662B-page 90
CRC Field ................................................................... 32
Data Field.................................................................... 32
Destination Address .................................................... 32
Padding Field .............................................................. 32
Preamble/Start-of-Frame Delimiter ............................. 31
Source Address .......................................................... 32
Type/Length Field ....................................................... 32
Reading....................................................................... 19
Scanning ..................................................................... 19
Writing ......................................................................... 19
Associated Registers .................................................. 73
Broadcast .................................................................... 52
Hash Table.................................................................. 52
Magic Packet .............................................................. 52
Magic Packet Format .................................................. 52
Multicast ...................................................................... 52
Pattern Match.............................................................. 51
Pattern Match Filter Format ........................................ 51
Unicast ........................................................................ 51
Using AND Logic......................................................... 50
Using OR Logic ........................................................... 49
Associated Registers .................................................. 46
Calculating Buffer Free Space .................................... 45
Calculating Free Receive Buffer Space ...................... 45
Calculating Random Access Address ......................... 44
Freeing Buffer Space .................................................. 45
Reading....................................................................... 44
Status Vectors............................................................. 44
EBSTCON (Ethernet Self-Test Control)...................... 75
ECOCON (Clock Output Control) ................................. 6
ECON1 (Ethernet Control 1) ....................................... 15
ECON2 (Ethernet Control 2) ....................................... 16
EFLOCON (Ethernet Flow Control) ............................ 56
EIE (Ethernet Interrupt Enable)................................... 65
EIR (Ethernet Interrupt Request, Flag) ....................... 66
ERXFCON (Ethernet Receive Filter Control) .............. 48
ESTAT (Ethernet Status) ............................................ 64
MABBIPG (MAC Back-to-Back
MACON1 (MAC Control 1).......................................... 34
MACON3 (MAC Control 3).......................................... 35
MACON4 (MAC Control 4).......................................... 36
MICMD (MII Command) .............................................. 21
MISTAT (MII Status) ................................................... 21
PHCON1 (PHY Control 1)........................................... 61
Inter-Packet Gap)................................................ 36
Preliminary
Reset .................................................................................. 59
S
Serial Peripheral Interface. See SPI.
SPI
System Reset ..................................................................... 60
T
Termination Requirement ..................................................... 7
Timing Diagrams
Transmit Buffer ................................................................... 17
Transmit Only Reset ........................................................... 60
Transmitting Packets .......................................................... 39
Typical ENC28J60-Based Interface...................................... 4
U
Unicast Filter....................................................................... 51
W
WWW, On-Line Support ....................................................... 2
PHCON2 (PHY Control 2) .......................................... 37
PHID (PHY Device ID)................................................ 22
PHIE (PHY Interrupt Enable) ...................................... 67
PHIR (PHY Interrupt Request, Flag)........................... 67
PHLCON (PHY Module LED Control)........................... 9
PHSTAT1 (Physical Layer Status 1)........................... 23
PHSTAT2 (Physical Layer Status 2)........................... 24
MAC and PHY Subsystem Resets ............................. 61
Power-on Reset .......................................................... 60
Receive Only Reset .................................................... 60
System Reset ............................................................. 60
Transmit Only Reset ................................................... 60
Bit Field Clear Command............................................ 29
Bit Field Set Command............................................... 29
Instruction Set............................................................. 26
Overview..................................................................... 25
Read Buffer Memory Command ................................. 28
Read Control Register Command............................... 27
System Reset Command............................................ 30
Write Buffer Memory Command ................................. 29
Write Control Register Command............................... 28
CLKOUT Transition ...................................................... 6
Read Control Register Command (ETH) .................... 27
Read Control Register Command (MAC/MII) ............. 27
SPI Input ..................................................................... 82
SPI Input Timing ......................................................... 25
SPI Output .................................................................. 82
SPI Output Timing ...................................................... 25
System Reset Command Sequence........................... 30
Write Buffer Memory Command Sequence ................ 29
Write Control Register Command Sequence.............. 28
Associated Registers .................................................. 42
Status Vectors ............................................................ 41
© 2006 Microchip Technology Inc.