adm6993 Infineon Technologies Corporation, adm6993 Datasheet - Page 36

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adm6993

Manufacturer Part Number
adm6993
Description
Adm6993/x Hdlc To Fast Ethernet Converter
Manufacturer
Infineon Technologies Corporation
Datasheet

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Table 20
Mode
Interrupt high,
self clearing
Interrupt low,
self clearing
Interrupt high,
mask clearing
Interrupt low,
mask clearing
Interrupt enable
register
latch_on_reset
Read/write
self clearing
Table 21
Clock Short Name
4.2.1
Signature Register
SR
Signature Register
Field
Signature
Port Configuration Register 0
Data Sheet
Register Access Types (cont’d)
Registers Clock DomainsRegisters Clock Domains
EEPROM Register Format
Bits
15:0
Symbol Description HW
ihsc
ilsc
ihmk
ilmk
ien
lor
rwsc
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
Differentiate the input signal (high-
>low) register cleared with written mask
Differentiate the input signal (low-
>high) register cleared with written
mask
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Type
ro
Description
Description
Signature
4154
H
SIG, Default (AT)
Offset
00
36
H
Description SW
SW can read the register
SW can read the register
SW can read the register, with write mask
the register can be cleared
SW can read the register, with write mask
the register can be cleared
SW can read and write this register
Register is read and writable by SW
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Registers Description
Rev 1.11, 2005-11-28
ADM6993/X
Reset Value
4154
H

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