lan9115 Standard Microsystems Corp., lan9115 Datasheet - Page 34

• Manufacturer Part Number: lan9115
• Description: Lan9115 Highly Efficient Single-chip 10/100 Non-pci Ethernet Controller
• Manufacturer: Standard Microsystems Corp.

Revision 1.5 (07-11-08)
3.9.2.1
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
page 95
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
for E2P_CMD field settings for each command.
Busy Bit = 0
EEPROM Write
Figure 3.3 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
34
Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
SMSC LAN9115
Datasheet