peb2025 ETC-unknow, peb2025 Datasheet - Page 11
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peb2025
Manufacturer Part Number
peb2025
Description
Isdn Exchange Power Controller
Manufacturer
ETC-unknow
Datasheet
1.PEB2025.pdf
(21 pages)
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Address Table
CS
0
0
0
0
1
Write Register
The write register is organized as shown below:
Automatic Restart Bit: Automatic restart mode is only possible in connection with the time-
dependent-current limitation, i.e. an external capacitor must be connected between pin CLCi and
GND. If D0i is high, automatic restart mode is enabled.
AR enabled
AR disabled
Semiconductor Group
D2i
D1i
A1
0
0
1
1
x
D2i
0
0
D0i
D1i
x
x
A0
0
1
0
1
x
D0i - D2i are bit 0 - 2 of line i
(line number i = 0 - 3)
Automatic Restart-Bit (AR)
ON/OFF-Bit (ON)
must be 0
11
D0i
1
0
Selected Line
Line 0
Line 1
Line 2
Line 3
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PEB 2025