m66256fp Renesas Electronics Corporation., m66256fp Datasheet
m66256fp
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m66256fp Summary of contents
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... Line Memory (FIFO) Description The M66256FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120-word × 8-bit configuration which uses high-performance silicon gate CMOS process technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between devices with different data processing throughput ...
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... M66256FP Pin Arrangement Data output Read enable input Read reset input Read clock input Data output REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Page M66256FP RRES WRES 6 19 GND ...
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... M66256FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature Recommended Operating Conditions Item Supply voltage Supply voltage Operating ambient temperature Electrical Characteristics Item "H" input voltage "L" input voltage "H" output voltage " ...
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... M66256FP Switching Characteristics Item Access time Output hold time Output enable time Output disable time Timing Conditions Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) " ...
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... M66256FP Test Circuit pF Input pulse level Input pulse rise/fall time Decision voltage input: 1.3 V Decision voltage output: 1.3 V (However, t decision) The load capacitance C includes the floating capacitance of connection and the input capacitance of probe. L Parameter t ODIS (LZ) t ODIS (HZ) ...
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... M66256FP Operating Timing Write Cycle Cycle n Cycle WCK t t WCK WCKH (n) Write Reset Cycle Cycle n − 1 Cycle n WCK t t WCK NRESH WRES − REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Page Cycle Disable cycle ...
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... M66256FP Matters that Needs Attention when WCK Stops n cycle cycle WCK t WCK (n) Period for writing data (n) into memory Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period cycle ...
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... M66256FP Read Cycle Cycle n Cycle RCK t t RCK RCKH RE Qn (n) Read Reset Cycle Cycle n − 1 Cycle n RCK t t RCK NRESH RRES (n − REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Page Cycle Disable cycle RCKL REH NRES NREH t ODIS ...
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... M66256FP Variable Length Delay Bits 1-line (5120 Bits) Delay A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily. ...
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... M66256FP N-bit Delay 2 (Sliding WRES and RRES at a cycle corresponding to delay length) Cycle 0 Cycle 1 WCK RCK t t RESS RESH WRES RRES (0) Qn N-bit Delay 3 (Disabling cycle corresponding to delay length) Cycle 0 Cycle 1 WCK RCK t t RESS RESH WRES RRES ...
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... M66256FP Shortest Read of Data "n" Written in Cycle n (Cycle n − read side should be started after end of cycle write side) When the start of cycle n − read side is earlier than the end of cycle write side, output Qn of cycle n becomes invalid. ...
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... M66256FP Application Example Laplacian Filter Circuit for Correction of Resolution in the Secondary Scanning Direction M66256 Line ( image data 1-line delay M66256 1-line delay Primary scanning direction REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Page Line n image data ...
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... M66256FP Package Dimensions 24P2U-A EIAJ Package Code JEDEC Code SSOP24-P-375-0.80 — Detail G 1 REJ03F0250-0200 Rev.2.00 Sep 14, 2007 Page Weight(g) Lead Material 0.4 Cu Alloy Detail F Plastic 24pin 375mil SSOP Recommended Mount Pad ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...