m66271fp Renesas Electronics Corporation., m66271fp Datasheet

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... M66271FP Operation Panel Controller Description The M66271FP is a graphic display-only controller for displaying a high duty dot matrix type LCD which is used widely for PPC, FAX and multi-function telephones capable of controlling a monochrome STN LCD system 320 × 240 dots. The IC has a built-in 9600-byte VRAM as a display data memory. ...

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... M66271FP Block Diagram MPU address A <13:0> Address bus 26 buffer : Data D <15:0> MPU data bus buffer 53 : Control register IOCS 2 chip select MCS VRAM chip select 6 HWR High write strobe 3 LWR Low write strobe 4 MPU I/F RD Read strobe 5 control MPUSEL 8/16 MPU select 12 circuit RESET ...

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... UD <1> 70 LCD display data bus UD <2> <3> 72 N.C 73 N.C 74 N Oscillator input OSC1 78 OSC2 Oscillator output REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page M66271FP (Top view) Outline: PRQP0080GB-A (80P6N- N.C 38 N.C N N <13> <12> <11> ...

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... M66271FP Pin Description Input/ Item Pin Name Output MPU D <15:0> Input/ MPU data bus interface Output Connect to MPU data bus. Selecting 8-bit MPU by MPUSEL input, D <15:8> connect <13:0> Input MPU address bus Connect to MPU address bus. When selecting 8-bit MPU, use A <13:0>. And selecting16-bit MPU, use A <13:1> for the address bus with combining A <0> and BHE by the method of access to internal VRAM (Refer to figure 1). Use A < ...

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... M66271FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Output current Power dissipation Storage temperature Recommended Operating Conditions Item Supply voltage V Supply voltage V Input voltage V Output voltage V Operating temperature Topr Electrical Characteristics Item High-level input voltage All inputs except for ...

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... M66271FP Switching Characteristics Item IOCS data access time MCS data access time RD data access time Output disable time after IOCS Output disable time after MCS Output disable time after RD WAIT output propagation time after MCS WAIT output propagation time after WR WAIT output propagation time after RD ...

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... M66271FP (2) Accessing to VRAM Item MCS pulse width WR pulse width Data set up time before falling edge of MCS Data set up time before falling edge of WR Data hold time after rising edge of MCS Data hold time after rising edge of WR Address set up time before falling edge of MCS ...

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... M66271FP Outline M66271FP is graphic display only controller for displaying a dot matrix type LCD. This IC has a built-in display data memory (VRAM) which is equivalent to 320 × 240 dots LCD. • Control register When access the control register from MPU side, use IOCS, LWR, RD, A <4:0> and D <7:0>. Refer to table 1, when set control type inputs ...

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... M66271FP Difference in VRAM between 8-bit and 16-bit MPU (1) When accessing built-in VRAM by 8-bit MPU (MPUSEL = "L", BHE = "H", HWR = "H": set) A <13:0> MCS LWR D <7:0> RD (2) When accessing built-in VRAM by 16-bit MPU (2-1) In case MPU use A <0> and BHE for byte access (MPUSEL = " ...

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... M66271FP Combination of Control Input Pins for MPU Interface Table show conditions of input setting when access the control register and VRAM from MPU. (1) Access control register (Use address = A <4:0>, Data = D <7:0>) Table 1 IOCS LWR (2) Writing to VRAM (2-1) When use 8-bit MPU (MPUSEL = "L", BHE = HWR = "H": set) ...

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... M66271FP (3) Reading from VRAM (3-1) When use 8-bit MPU (MPUSEL = "L", BHE = "H": set) Table 5 MPU MCS BHE SEL A <0> (3-2) When use 16-bit MPU (MPUSEL = ''H": set) Table 6 MPU MCS BHE SEL A <0> Note: Avoid setting combination except above, as cause of error action. ...

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... M66271FP Description of Cycle Steal Basic Timing Basic timing of M66271FP is two clocks of OSC (internal clock after dividing OSC1 input). Assign first clock to accessing from MPU to VRAM and second clock to transferring of display data from VRAM to LCD. OSC (Internal clock after dividing OSC1 input) ...

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... M66271FP Function of Cycle Steal Control M66271FP has a function for processing data of a line with more efficient. This function access with the cycle steal method as taking WAIT for MPU during the display term with necessity for the display data transfer from built-in VRAM to LCD ...

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... M66271FP Additional Function for LCD Module Built-in System As all of the VRAM address in M66271FP are externally opened for addressing VRAM from MPU directly. When consider the LCD module built-in system, connect pins are increased. But M66271FP has an additional function for the LCD module built-in system by lessening connect pins. ...

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... M66271FP Control Register M66271FP has 9 kinds of control register. To set mode from MPU to control register, use IOCS, LWR, RD, A <4:0> and D <7:0>. (1) Kind of control register Control Register Table Kind of Register Address No. Name Mode register Horizontal display character ...

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... M66271FP (2) Description of register (2-1) Mode register [R1] Address R/W 00000 R Only "R" wait access 1 Cycle steal access D6 0 Reset OFF 1 Reset ON OSCC REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page Function • Status register for identifying active or inactive in cycle steal function ...

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... M66271FP (2-2) Horizontal display characters number register [R2] Address R/W 00010 • The number of horizontal display characters per line can set to the extent of Max = 504 dots (= 63 characters) • When reset "28 Note: Definition of the number of display characters. The number of display characters means data which is corresponding with 1 byte of VRAM. ...

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... M66271FP (2-4) Cycle steal enable width register [R4] Address R/W 00110 • During the horizontal synchronous term, set term of access by cycle steal method in character number unit. Setting value of CSW sets below LPW value. • When reset, CSW = "00 Note: Be careful with first and second byte of display data UD < ...

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... M66271FP (2-6) Display start address register [R6, R7] Address R/W 01010 R/W SAL • D6 and D7 output "0" when read SAH. • possible to set display start address to the extent of 257F 01100 • Don't set over 2580 SAH • ...

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... M66271FP (2-9) VRAM address index register [R10, R11] Address R/W 10010 R/W IDXL IDXH 10100 • IDXH Exclusive VRAM address index register for the LCD module built-in system. • possible to change the register only one side, because IDXH and IDXL are independent each other. • ...

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... M66271FP Relation between Address of VRAM and LCD Display ex. 1) When display start address = 0000 0000 0001 H H VRAM 9600-byte 257E ex. 2) When display start address = 1000 0000 0001 H H VRAM 9600-byte 1000 1001 H H 257E Remark) VRAM address counter return to "0000 after count up address to " ...

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... M66271FP Output Signal of LCD Side Ex.) Assuming 320 × 240 dots LCD (In setting characters, LPW = 2 characters, SLT = 240 lines, OSCC = 1 division toggle per line) (1) Output signal per line OSC1 <3:0> LP (2) Output signal per frame 239 240 1 LP FLM ...

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... M66271FP Timing Diagram (1) Write to Control Register (RD = "H") Without WAIT IOCS LWR WAIT tsu (D-IOCS) tsu (D-LWR) D <7:0> tsu (A-IOCS) tsu (A-LWR) A <4:0> (2) Read from Control Register (LWR = "H") Without WAIT IOCS RD WAIT D <7:0> tsu (A-IOCS) tsu (A-RD) A <4:0> Note: 1. Writing/Reading operation for the control register is performed during overlapping IOCS and (LWR or RD). ...

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... M66271FP (3) Write to VRAM (RD = "H") Term of non cycle steal access MCS LWR (+HWR) WAIT tsu (D-MCS) tsu (D-WR) D <7:0> (D <15:0>) tsu (A-MCS) tsu (A-WR) A <13:0> (+BHE) (4) Read from VRAM (LWR, HWR = "H") Term of non cycle steal access MCS RD WAIT D <7:0> (D <15:0>) tsu (A-MCS) tsu (A-RD) A <13:0> ...

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... M66271FP (5) Write to VRAM (RD = "H") Term of cycle steal access MPUCLK MCS LWR (+HWR) WAIT tsu (D-MCS) D <7:0> (D <15:0>) tsu (A-MCS) tsu (A-WR) A <13:0> (+BHE) (6) Read from VRAM (LWR, HWR = "H") Term of cycle steal access MPUCLK MCS RD WAIT D <7:0> (D <15:0>) tsu (A-MCS) tsu (A-RD) A <13:0> Notes: 3. Reading/writing operation for VRAM during cycle steal needs 1 tc (Internal) in best case (Internal) in worst case, according to the condition of the internal cycle steal at starting access requested from MPU ...

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... M66271FP (7) Interface Timing with LCD (OSCC = 1 division: set) 1. Transfer of LCD display data OSC1 tpd (OSC-CP (CP <3:0> 2. LCD control signal OSC1 CP LP FLM (OSC-LE) LCDENB Note: 6. Output signal to LCD side is synchronized with OSC clock for internal operation. When division is set to 1/2 to 1/16 by OSCC register, switching characteristics is defined by rising edge of OSC1 ...

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... M66271FP Package Dimensions JEITA Package Code RENESAS Code P-QFP80-14x20-0.80 PRQP0080GB Index mark y e REJ03F0267-0200 Rev.2.00 Mar 18, 2008 Page Previous Code MASS[Typ.] 80P6N-A 1. NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. ...

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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...