psb21391 Infineon Technologies Corporation, psb21391 Datasheet - Page 168

• Manufacturer Part Number: psb21391
• Description: Siemens Codec With Upn Transceiver
• Manufacturer: Infineon Technologies Corporation

Data Sheet
5.1
5.1.1
The receive PLL readjusts, if the integrator function is enabled (TR_CONF1.RPLL_INTD
= ’0’) if six consecutive pulses on the U
integrator function is disabled by setting TR_CONF1.RPLL_INTD to ’1’ this is done after
the deviation of every pulse. Adjusting on the positive and negative pulses is done by
adding/subtracting 1 XTAL from/to the DCL clock.
5.1.2
The U
5.1.3
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers
are involved.
Figure 79 Clock waveforms
PN
transmit clock is derived from the U
Jitter
Jitter on IOM-2
Jitter on U
Jitter on MCLK
FSC
DCL
BCL
PN
PN
158
interface deviate in the same direction. If the
PN
receive clock.
Clock Generation
PSB 21391
PSB 21393
2001-03-07