saf-xc836t-2fri Infineon Technologies Corporation, saf-xc836t-2fri Datasheet - Page 48

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saf-xc836t-2fri

Manufacturer Part Number
saf-xc836t-2fri
Description
8-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
3.3.5
3.3.5.1
Table 22
Table 22
Parameter
SCLK clock period
MTSR delay from SCLK
MRST set-up to SCLK
MRST hold from SCLK
1) Not subject to production test, verified by design/characterisation.
2) T
Figure 15
Data Sheet
SSCmin
= T
provides the SSC master mode timing in the XC835/836.
SSC Timing
SSC Master Mode Timing
CPU
SCLK
MTSR
MRST
SSC Master Mode Timing
SSC Master Mode Timing
= 1/
1)
1)
1)
1) This timing is based on the following setup: CON.PH = CON.PO = 0.
f
CPU
. When
f
CPU
t
t
1
1
= 24 MHz,
t
2
Data
t
valid
0
Symbol
t
t
t
t
t
0
1
2
3
= 83.3 ns. T
0
1)
t
3
43
(Operating Conditions apply; CL = 50 pF)
CC
CC
SR
SR
CPU
is the CPU clock period.
Min.
2 * T
0
32
0
t
1
SSC
Limit Values
2)
Electrical Parameters
SSC_Tmg1
Max.
3
XC835/836
V1.0, 2010-09
Unit
ns
ns
ns
ns

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