adm1075-2aruz-rl7 Analog Devices, Inc., adm1075-2aruz-rl7 Datasheet - Page 23

• Manufacturer Part Number: adm1075-2aruz-rl7
• Description: −48 V Hot Swap Controller And Digital Power Monitor With Pmbus Interface
• Manufacturer: Analog Devices, Inc.

Data Sheet
the PLIM pin, the relationship of V
The foldback voltage, V
reference selector block and is defined as
The resistor divider should be designed to generate a V
voltage equal to I
rises above the desired power level. If I
be 0.1 V at the point where constant power takes over (V
I
10 A current limit, the maximum V
the current limit. Therefore, the resistor divider must be 200:1
to generate a 0.1 V PLIM voltage at V
continues to increase, the current limit reference follows V
because it is now the lowest voltage input to the current limit
reference selector block. This results in a reduction of the
current limit, and, therefore, the regulated load current. To
prevent complete current flow restriction, a clamp becomes
active when the current limit reference reaches 100 mV. The
current limit cannot drop below this level. This 200 W constant
power example is illustrated in terms of FET SOA and real
scope plots in Figure 48 and Figure 49.
When V
regulation current through the FET is
where I
amplifier gain.
where D is the resistor divider factor on PLIM.
Therefore, the FET power is calculated as
Because P
constant. Therefore, the FET power for a given system can be
set by adjusting the divider (D) driving the PLIM pin.
The limits to the constant power system are when V
1 V if V
clamp on V
foldback current range.
SET
). For example, to generate a 200 W constant power limit at
V
I
I
I
P
D
D
D
FET
FLB
= V
= 0.1/( V
= 0.1/( V
D
ISET
FLB
is the external FET drain current, and Gain is the sense
= I
= 0.1/ V
FET
FLB
> V
has control of the current limit reference, the
CLREF
D
does not have any dependency on V
/( Gain × R
× V
ISETRSTH
PLIM
DS
). With an I
PLIM
SET
DS
× D × Gain × R
× Gain × R
= 0.1/( D × Gain × R
when the V
) or when V
FLB
SENSE
, is the input to the current limit
SET
)
voltage of 1 V, this gives a 10:1
SENSE
DS
SENSE
FLB
of the FET (and thus V
)
DS
DS
< 100 mV (100 mV max
DS
)
to V
is required to be 20 V at
SET
= 20 V. As V
SENSE
= 1 V, V
PLIM
)
can be controlled.
DS
PLIM
, it remains
FLB
PLIM
needs to
> I
FLB
FLB
PLIM
SET
FLB
=
)
Rev. 0 | Page 23 of 52
(or
TIMER
The TIMER pin handles several timing functions with an
external capacitor, C
V
sources are a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down,
and a 100 μA pull-down.
These current and voltage levels, together with the value of
C
time, the fault current limit time, and the hot swap retry duty
cycle. The TIMER capacitor value is determined using the
following equation:
where t
regulation. The choice of C
with the SOA requirements of the FET. Foldback can be used
here to simplify selection.
When V
supply of the
later when the internal supply is fully up and above the undervolt-
age lockout voltage (UVLO), the device comes out of reset.
During this first short reset period, the GATE and TIMER pins
are both held low. The
TIMER
TIMERH
Figure 49. 200 W Constant Power Scope Plot, CH1 = VIN; CH2 = V
C
1000
3,4
1,2
100
M1
TIMER
0.1
chosen by the user, determine the initial timing cycle
10
ON
1
(1.0 V) and V
0.1
IN
is the time that the FET is allowed to spend in
CH3 = GATE; CH4 = System Current; M1 = FET Power
is connected to the backplane supply, the internal
= ( t
ADM1075
ON
× 60 μA)/ V
DISSIPATION
MAX 200W
POWER
TIMER
1
TIMERL
ADM1075
20V × 10A = 200W
Figure 48. FET SOA
must be charged up. A very short time
. There are two comparator thresholds:
CURRENT LIMIT ADJUSTING
TIMER
60V × 3.33A = 200W
(0.05 V). The four timing current
TIMERH
V
V
DS
DS
is based on matching this time
10
(V)
VIN
then goes through an initial
200W CONSTANT POWER
100
1µs
10µs
100µs
1ms
10ms
DC
I
ADM1075
IN
GATE
1000
DS
;