cyv15g0204trb Cypress Semiconductor Corporation., cyv15g0204trb Datasheet - Page 13

• Manufacturer Part Number: cyv15g0204trb
• Description: Independent Clock Hotlink Ii Dual Serializer And Dual Reclocking Deserializer
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-02101 Rev. *B
Table 1. Operating Speed Settings
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Transmit Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50Ω transmission lines. These drivers accept data from the
Transmit Shifters. These drivers have signal swings equivalent
to that of standard PECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note. When a disabled transmit channel (i.e., both outputs
disabled) is re-enabled:
Note:
7.
• data on the serial outputs may not meet all timing specifi-
• the state of the phase-align buffer cannot be guaranteed,
MID (Open)
SPDSELx
cations for up to 250 µs
and a phase-align reset is required if the phase-align buffer
is used
The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
HIGH
LOW
TXRATEx
1
0
1
0
1
0
REFCLKx±
Frequency
reserved
19.5–40
80–150
20–40
40–75
(MHz)
40–80
Rate (Mbps)
Signaling
800–1500
195–400
400–800
CYV15G0204TRB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1± and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VI
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal DC-
restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELx latch via device configuration interface. The
SDASELx latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in Table 2. This control
input affects the analog monitors for both receive channels.
The Analog Signal Detect monitors are active for the Line
Receiver as selected by the associated INSELx input.
Table 2. Analog Amplitude Detect Valid Signal Levels
SDASEL Typical Signal with Peak Amplitudes Above
• analog amplitude above amplitude level selected by
• transition density above the specified limit
• range controls report the received data stream inside
• receive channel enabled
• Presence of reference clock
• ULCx is not asserted.
SDASELx
normal frequency range (±1500 ppm
00
01
10
11
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
DIFF
> 100 mV, or 200 mV peak-to-peak
CYV15G0204TRB
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