max2036ccq Maxim Integrated Products, Inc., max2036ccq Datasheet - Page 17

• Manufacturer Part Number: max2036ccq
• Description: Ultrasound Vga Integrated With Cw Octal Mixer
• Manufacturer: Maxim Integrated Products, Inc.

The LO_LVDS input frequency is 8 x f
2 operation. The CWD LO frequency range is 1MHz to
7.5MHz, and the input frequency ranges from 8MHz to
60MHz. This high LO clock frequency requires a differ-
ential LVDS input. The 8 x f
to produce 8 phases. These 8 phases are generated
for each of the 8 channels and programmed for the
selected phase by the serial shift register. Note that the
serial shift register is common to modes 1, 2, and 3,
where each channel has a corresponding 5-bit shift
register, which is used to program the output phase.
However, since mode 2 generates 8 phases only, 3 of
the 4 phase-programming bits are used; 5 bits are still
loaded per channel using the serial shift register, but
the phase-programming MSB is a don’t-care bit. The
fifth bit in the shift register always turns each channel
on/off individually. For mode 2, set CW_M1 to a logic-
low and set CW_M2 to a logic-high. See Table 3.
The LO_LVDS input is not used in this mode. Separate
4 x f
each channel. The CWD LO frequency range is 1MHz to
7.5MHz, and the input frequency provides ranges from
4MHz to 30MHz. Note that the LO clock frequency can
utilize 3V CMOS inputs. The 4 x f
divided by 4 to produce 4 phases. These 4 phases are
Table 3. Mode 2 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
CW_M1 = 0
CW_M2 = 1
MODE 2
PHASE
(DEG)
135
180
225
270
315
LO
45
90
0
clock inputs are provided using LO1–LO8 for
(B0)
DC
DC
DC
DC
DC
DC
DC
DC
D
______________________________________________________________________________________
(B1)
C
0
0
0
0
1
1
1
1
LO
(B2)
input is then divided by 8
B
0
0
1
1
0
0
1
1
LO
LO1–LO8 inputs are
(B3)
LO
A
0
1
0
1
0
1
0
1
(typ) for mode
SHUTDOWN
(B4)
Mode 2
Mode 3
SD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
Ultrasound VGA Integrated
generated for each of the 8 channels and programmed
for the selected phase by the serial shift register. For
mode 3, 4 phases are generated, and only 2 of the 4
phase-programming bits are required where the 2-
phase programming MSBs are don’t-care bits. For
mode 3, set CW_M1 to a logic-high and set CW_M2 to
a logic-low. See Table 4.
The LO_LVDS input is not used in this mode. The
appropriate phases are externally provided using sepa-
rate 4 x f
input is required so the device can internally generate
accurate duty-cycle independent quadrature LO drives.
Note that the serial shift register is not used in this
mode. The CWD LO frequency range is 1MHz to
7.5MHz and the input frequency ranges from 4MHz to
30MHz. The appropriate inputs are provided at LO1 to
LO8. A reset line is provided to the customer so that all
the CWD channels can be synchronized. The reset line
is implemented through the RESET. For mode 4, set
both CW_M1 and CW_M2 to logic-high. See Table 5.
Table 4. Mode 3 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
Table 5. Mode 4 Logic Table
N/A = Not applicable.
Serial bus
not used in
mode 4
CW_M1 = 1
CW_M2 = 0
CW_M1 = 1
CW_M2 = 1
MODE 3
MODE 4
PHASE
PHASE
(DEG)
(DEG)
180
270
90
0
with CW Octal Mixer
LO
LO1–LO8 inputs for each channel. A 4 x f
(B0)
(B0)
N/A
DC
DC
DC
DC
D
D
(B1)
(B1)
N/A
DC
DC
DC
DC
C
C
(B2)
(B2)
N/A
B
0
0
1
1
B
(B3)
(B3)
N/A
A
A
0
1
0
1
SHUTDOWN
SHUTDOWN
(B4)
(B4)
Mode 4
N/A
SD
0/1
0/1
0/1
0/1
SD
17
LO