amis-30523 ON Semiconductor, amis-30523 Datasheet - Page 31

• Manufacturer Part Number: amis-30523
• Description: Amis-30523 Product Preview Can Micro-stepping Motor Driver
• Manufacturer: ON Semiconductor

Where:
R/W
Reset:
18. The typical values can be found in Table 5: DC Parameters Motor Driver and in Table 6: AC parameters Motor Driver
Table 14. SPI CONTROL REGISTERS
hard reset.)
Table 15. SPI CONTROL PARAMETER OVERVIEW
CR0 (01h)
CR1 (02h)
CR2 (03h)
WR (00h)
Address
DIRCTRL
EMC[1:0]
Symbol
MOTEN
SM[2:0]
PWMF
PWMJ
NXTP
SLAG
SLAT
SLP
Content
Access
(in combination with logic level on input DIR)
Reset
Data
Data
Data
Data
Read and Write access
Status after power−On or hard reset
Turn On – Turn−off Slopes of motor driver
Selects if NXT triggers on rising or falling
Enables doubling of the PWM frequency
Speed load angle transparency bit
Activates the motor driver outputs
Controls the direction of rotation
Speed load angle gain setting
Enables sleep mode
Enables jittery PWM
DIRCTRL
MOTEN
WDEN
Bit 7
R/W
Description
Stepmode
0
(Note 18)
(Note 18)
edge
SM[2:0]
(All SPI control registers have Read/Write Access and default to ”0” after power−on or
NXTP
Bit 6
R/W
SLP
0
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SLAG
Bit 5
R/W
0
−
WDT[3:0]
<MOTEN> = 0
<MOTEN> = 1
31
<PWMF> = 0
<PWMF> = 1
<PWMJ> = 0
<PWMJ> = 1
<NXTP> = 0
<NXTP> = 1
<SLAG> = 0
<SLAG> = 1
<SLAT> = 0
<SLAT> = 1
<SLP> = 0
<SLP> = 1
<DIR> = 0
<DIR> = 1
000
001
010
011
100
101
110
111
00
01
10
11
SLAT
Bit 4
R/W
0
−
Structure
Status
PWMF
Bit 3
R/W
<DIRCTRL> = 0
<DIRCTRL> = 1
<DIRCTRL> = 0
<DIRCTRL> = 1
0
−
Uncompensated Half Step
SLA is NOT transparent
Compensated Half Step
CUR[4:0]
Trigger on falling edge
Trigger on rising edge
PWMJ
Bit 2
SLA is transparent
Default Frequency
Double Frequency
R/W
1/32 Micro − Step
1/16 Micro − Step
1/8 Micro − Step
1/4 Micro − Step
Drivers disabled
Drivers enabled
0
−
−
Jitter disabled
Jitter enabled
Active mode
Sleep mode
Gain = 0.25
Gain = 0.5
Very Slow
Very Fast
Full Step
Slow
Fast
n.a.
Bit 1
R/W
0
−
−
CCW motion
CCW motion
CW motion
CW motion
EMC[1:0]
Value
Bit 0
R/W
0
−
−