sta015t-013tr STMicroelectronics, sta015t-013tr Datasheet - Page 44
sta015t-013tr
Manufacturer Part Number
sta015t-013tr
Description
Mpeg 2.5 Layer Iii Audio Decoder With Adpcm Capability
Manufacturer
STMicroelectronics
Datasheet
1.STA015T-013TR.pdf
(55 pages)
- Current page: 44 of 55
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STA015 STA015B STA015T
ADC_WLEN
Address: 0xC0 (192)
Type: R/W
Software Reset: 0x0F
Hardware Reset: 0x0F
To select ADC word length AWL4 through AWL0 bits can be used.
This 5 bit value must contain the size of the significant data bits minus one.
ADC_WPOS
Address: 0xC1 (193)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
These bits specify the position of the sample word referred to the LRCK slot boundary.
Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word.
ADPCM_SKIP_FRAME
Address: 0xC2 (194)
Type: R/W
Software Reset:0x00
Hardware Reset: 0x00
This register is useful when decoding ADPCM frame-based streams in order to skip the specified number
of frames.
The content of the register will automatically be decremented on each new frame and the skip process will
continue until the content reaches zero.
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ASF7
MSB
MSB
MSB
b7
b7
b7
X
X
ASF6
b6
b6
b6
X
X
ASF5
b5
b5
b5
X
X
AWP4
AWL4
ASF4
b4
b4
b4
AWP3
AWL3
ASF3
b3
b3
b3
AWP2
AWL2
ASF2
b2
b2
b2
AWP1
AWL1
ASF1
b1
b1
b1
AWP0
AWL0
ASF0
LSB
LSB
LSB
b0
b0
b0
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