sta002 STMicroelectronics, sta002 Datasheet - Page 7

• Manufacturer Part Number: sta002
• Description: Starmano Channel Decoder
• Manufacturer: STMicroelectronics

for synchronisation. The STA002 is always a
slave device in all its communications.
1. 1 COMMUNICATION PROTOCOL
1.1.0 Data transition or change
Data changes on the SDA line must only occur
when the SCL clock is low. SDA transitions while
the clock is high are used to identify START or
STOP condition.
1.1.1 Start condition
START is identified by a high to low transition of
the data bus SDA signal while the clock signal
SCL is stable in the high state. A START condi-
tion must precede any command for data transfer.
1.1.2 Stop condition
STOP is identified by low to high transition of the
data bus SDA signal while the clock signal SCL is
stable in the high state. A STOP condition termi-
nates communications between STA002 and the
bus master.
1.1.3 Acknowledge bit
An acknowledge bit is used to indicate a success-
ful data transfer. The bus transmitter, either mas-
ter or slave, will release the SDA bus after send-
ing 8 bits of data.
During the 9th clock pulse the receiver pulls the
SDA bus low to acknowledge the receipt of 8 bits
of data.
Some registers do not give acknowledge when
the data is not available.
1.1.4 Data input
During the data input the STA002 samples the
SDA signal on the rising edge of the clock SCL.
For correct device operation the SDA signal has
to be stable during the rising edge of the clock
and the data can change only when the SCL line
is low.
1.2 DEVICE ADDRESSING
To start communication between the master and
the STA002, the master must initiate with a start
condition. Following this the master sends onto
the SDA line 8 bits (MSB first) corresponding to
the device select address and read or write
mode.
The 7 most significant bits are the device address
identifier, corresponding to the I2C bus definition.
For the STA002 these are fixed as 1101010.
The 8th bit (LSB) is the read or write operation bit
(RW; set to 1 in read mode and to 0 in write
mode). After a START condition the STA002
identifies on the bus the device address and if
matching it will acknowledges the identification on
SDA bus during the 9th bit time.
The following 2 bytes after the device identifica-
tion byte are the internal space address.
1.3 WRITE OPERATION (see fig. 5)
Following a START condition the master sends a
device select code with the RW bit set to 0.
The STA002 gives the acknowledge and waits for
the 2 bytes of internal address. The least signifi-
cant 10 bits of the 2 bytes address provides ac-
cess to any of the internal registers. The most
significant bit means incremental mode (1 =
autoincremental, 0 = no) and the other bits are
set to zero.
After the receiption of each of the internal bytes
address the STA002 again responds with an ac-
knowledge.
1.3.1 Byte write
In the byte write mode the master sends one data
byte and this is acknowledged by STA002. The
master then terminates the transfer by generating
a STOP condition.
1.3.2 Multibyte write
The multibyte write mode can start from any inter-
nal address. The master sends the data and each
one is acknowledged by the STA002. The trans-
fer is terminated by the master generating a
STOP condition.
1.4 READ OPERATION (see Fig. 6)
1.4.1 Current byte address read
The STA002 has an internal byte address
counter. Each time a byte is written or read, this
counter, according to the autoincremental bit set-
ting, is incremented or not.
For the current byte address read mode, follow-
ing a START condition the master sends the de-
vice address with the RW bit set to 1. The
STA002 acknowledges this and outputs the byte
addressed by the internal byte address counter.
The counter is then incremented or not depend-
ing on the autoincremental bit. The master does
not acknowledge the received byte, but termi-
nates the transfer with a STOP condition.
1.4.2 Random byte address read
A dummy write is performed to load the byte ad-
dress into the internal address register.
STA002
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