z86131 ZiLOG Semiconductor, z86131 Datasheet - Page 24

• Manufacturer Part Number: z86131
• Description: Ntsc Line 21 Decoder
• Manufacturer: ZiLOG Semiconductor

Z86129/130/131
NTSC Line 21 Decoder
SERIAL COMMUNICATIONS INTERFACE
C o m m a n d s a n d d a t a a r e s e n t t o a n d f r o m t h e
Z86129/130/131 through its serial communications inter-
face. Two Serial Control Modes are available. One mode
is a two wire I
three wire, synchronous serial peripheral interface (SPI). In
both cases the Z86129/130/131 acts as a slave device.
This port is the path for setting the configuration and oper-
ational modes of the device. It is also the port for outputting
the recovered XDS data and for inputting the OSD data for
display.
Five pins are dedicated to the control port function and one
additional pin can be configured to provide an interrupt out-
put. These pins are designated as indicated in Table 14.
When the Vertical Lock = VIDEO, the V
is configured as an output, providing the INTRO signal.
This interrupt operation is available in either serial control
mode.
The Z86129/130/131 is able to interrupt on the occurrence
of any of several events. The master device clears the in-
terrupt by writing to the Interrupt Request Register.
I
The serial control mode in use is selected by the state of the
SMS pin. When SMS is set Low, the Z86129/130/131 is in
the I
ports a bidirectional two wire bus and data transmission pro-
tocol. The bus is controlled by the master device, which gen-
erates the serial clock (SCK), controls the bus access and
generates the Start and Stop conditions. The SDA pin is the
bidirectional Data line. In this mode, the SDO output is not
used, and the pin is in its high-impedance state.
The Z86129/130/131 can receive or transmit data under
control of the master device. The Z86129/130/131 is a slave
24
Signal
Pin #
I/O
I2C
SPI
Notes:
SMS = Serial Mode Select High = SPI & Low =
SCK = Serial port clock for either Serial Mode.
SDA = Serial port data for
SDO = Serial Data Out for SPI Mode. Not used in
SEN = SPI Mode Enable signal. Must be High for
2
C Bus Operation
Table 14. Z86129/130/131 Serial Control Signals
2
C mode. In this mode, the Z86129/130/131 also sup-
SMS
6
0
1
I
2
C bus interface. The other serial mode is a
SCK
CLK
CLK
15
I
I
2
C
Data In
Mode and Data In for SPI Mode.
SDA
Data
I/O
14
Data Out
SDO
Hi-Z
IN
16
O
/INTRO (pin13)
I
2
C.
I
I
2
2
C
C
P R E L I M I N A R Y
Enable
Mode.
Mode.
SEN
4
1
I
device. Communication is initiated when the master device
sends the start condition followed by the Z86129/130/131
Slave Address Read byte (29h) or Slave Address Write byte
(28h). The Z86129/130/131 responds with an Acknowl-
edge. The I
(LSB) of the I
I
Note:
the RESET state. Therefore the SEN pin can be used to reset the
part while in the I
SET signal or tied High if no reset is desired.
The I
1. Data transfer can only be started when the bus is not
2. During data transfer, data transitions must not occur
Bus Conditions
Bus Conditions are defined as:
Not Busy.
Start.
line is High.
Stop.
line is High.
Acknowledge.
output an acknowledge after the reception of each byte. The
master device must generate the clock for the acknowledge
bit. Acknowledge is SDA=Low. Not Acknowledge
(NACK) is SDA=High.
Data.
on the falling edge of SCK, MSB first. The receiving device
reads the data, MSB first, on the rising edge of SCK.
Communication with the Z86129/130/131 is initiated when
the master device sends the Z86129/130/131 slave address
following a start condition. The Z86129/130/131 has a pre-
set, single, seven-bit slave address. The Z86129/130/131
responds with an acknowledge. The eighth bit of the slave
address is driven High for Read operations and Low for
Write operations.
2
C Address
Table 15. Z86129/130/131 I
busy.
while the clock is High.
The data (SDA) is output by the transmitting device
2
A Low-to-High transition of SDA line while SCK
When the SMS and SEN pins are both Low, the part is in
A High-to-Low transition of SDA line while SCK
C Bus Protocol
Data and Clock lines both High.
2
C RD/nWR bit is the Least Significant Bit
2
C addresses listed Table 15.
2
When addressed, the receiving device must
C mode. The SEN pin may be tied to an NRE-
READ
29h
2
C Slave Addresses
DS007200-TVX0199
WRITE
28h
ZiLOG