qt60320d Quantum Research Group, qt60320d Datasheet - Page 5

• Manufacturer Part Number: qt60320d
• Description: 32-key Qmatrix? Charge-transfer Ic
• Manufacturer: Quantum Research Group

2 - CIRCUIT
SPECIFICS
A basic QT60320D circuit is
shown in Figure 2-1.
2.1 SIGNAL PATH
The QT60320D requires an
external sampling capacitor,
two Cz capacitors, an amplifier,
some analog switches, and an
R2R ladder DAC to operate.
The Cs capacitor performs the
charge integration function by
collecting charge coupled
though a selected key during
the dV/dt of the rising edge of
an 'X' scan line. The charge is
sampled 'n' times during the
course of a burst of switching
cycles of length 'n'. As the
burst progresses the charge on
Cs increases in a staircase
fashion (Figure 1-4).
At the burst's end the voltage
on Cs, which is on the order of
a few tenths of a volt, is
amplified by a gain circuit which includes an offset current
from the R2R ladder DAC driven by the X drive lines. The
offset current from the R2R ladder repositions the output of
the amplifier chain to coincide as closely as possible with the
center span of the 60320's ADC, which can convert voltages
LQ
Vcc
CAL L ED
STAT LED
UAR T IN
U ART OU T
D S 18 11
Figure 2-2 Improved Circuit to Suppress Water Films
8M H z
1 0
3 3
3 4
3 5
3 6
1 2
1 3
1 4
2 3
2 4
2 5
2 6
1 5
1 6
11
4
9
8
7
5 17 27
R st
R x
Tx
I 1
I 2
I 3
I 4
O 1
O 2
O 3
O 4
O 5
O 6
O 7
O 8
XT1
XT2
L 1
L 2
V
6 18
G G G G
V
Vcc
28
V
2 9
39
V
Y S3
CC 1
CC 2
YS1
Y S2
Y S4
AIN
3 8
CS
X2
X3
X4
X5
X6
X7
X8
V
21
40
41
42
43
44
1
2
3
20
22
32
31
30
37
19
Vcc
C6 (Cz 1) 820pF
CAL L ED
STAT LED
BSN 20
UART I N
U ART OUT
D S 18 11
C 7 (Cz 2) 820p F
R 2R dac 100K
8MHz
R 4 100 K
10
33
34
35
36
12
13
14
23
24
25
26
15
16
11
4
9
8
7
5 1 7 2 7
Rst
Rx
Tx
I1
I2
I3
I4
O 1
O 2
O 3
O 4
O 5
O 6
O 7
O 8
XT1
XT2
L1
L2
V
+
_
6 18
G
V
G G G
TLC 2272
Vcc
28
V
29
22 V10
39
V
YS3
CC 1
CC 2
YS2
YS4
R 3 68 K
R 6 10 K
YS1
AIN
38
C S
X1
X2
X3
X4
X5
X6
X7
X8
V
Figure 2-1 Basic QT60320D Circuit
21
_
4 0
4 1
4 2
4 3
4 4
1
2
3
1 9
2 0
2 2
3 2
3 1
3 0
3 7
+
C6 (Cz1) 8 20pF
5
BSN20
between 0 and 5 volts. Between bursts the Cs reset mosfet is
activated to reset the Cs capacitor to ground.
Gain is directly controlled by burst length 'n', amplifier gain
Av, and the values of Cs, Cz1 and Cz2. Only 'n' can be
adjusted on a key by key basis whereas Av and the
C7 (Cz2) 8 20pF
E
E
E
E
R 5 1 0K
R t
Y4
I /O
I /O
R 2R d ac 1 00K
C 5 (C s)
15nF
R4 100K
QS 31 25
Keym atr ix
Y 3
I/O
I/O
+
_
C t
Y 2
I /O
I /O
TL C22 72
R3 68K
R6 10K
Y1
I/O
I/O
_
+
R 5 10K
capacitances can only be adjusted
for all keys. The amplifier should
typically have a total positive gain
of 100 +/- 20%..
If there is a large amount of
coupling between X and Y lines,
and where burst length 'n' is set to
a
accumulation on Cs may reach a
point where the ladder DAC can no
longer offset the signal back into
the ADC's usable range. In this
case the circuit will employ one or
two of the Cz capacitors to 'knock
back'
accumulated on Cs; each Cz will
cancel charge in a discrete step as
required.
Y4
C5 (Cs)
1 5nF
Keymatrix
Y3
QT60320D R1.11/12.07.03
high
or
Y2
Y1
cancel
74 AC 04
number,
the
charge
charge