qt511 Quantum Research Group, qt511 Datasheet - Page 6

• Manufacturer Part Number: qt511
• Description: Qwheel? Touch Slider Ic
• Manufacturer: Quantum Research Group

2.6 ESD
Please refer to Quantum app note AN-KD02 for further
information on ESD and EMC matters.
3 Serial Communications
The serial interface is a SPI slave-only mode type which is
compatible with multi-drop operation, i.e. the MISO pin will
float after a shift operation to allow other SPI devices (master
or slave) to talk over the same bus. There should be one
dedicated /SS line for each QT511 from the host controller.
A DRDY (‘data ready’) line is used to indicate to the host
controller when it is possible to talk to the QT511.
3.1 Power-up Timing Delay
Immediately after power-up, DRDY floats for approximately
20ms, then goes low. The device requires ~525ms thereafter
before DRDY goes high again, indicating that the device has
calibrated and is able to communicate.
From power up to first communication, allow a total of 550ms
in startup delay.
3.2 SPI Timing
The SPI interface is a five-wire slave-only type; timings are
found in Figure 3-1. The phase clocking is as follows:
lQ
(Slave Input - MOSI)
Data out changes on:
(Slave Out - MISO)
Host Data Output
Data Ready DRDY:
QT Data Output
Input data read on:
DRDY from QT
CLK from Host
Bit length & order:
Acquire Burst
/SS from host
Slave Select /SS:
Sleep Mode
,
EMC and Related Issues
Clock rate:
Clock idle:
<10us delay
edge to data
3-state
?
awake
output driven
<12us after /SS
goes low
?
Data sampled on rising edge
Data shifts out on falling edge
7
7
High
Falling edge of CLK from host
Rising edge of CLK from host
Negative level frame from host
Low from QT inhibits host
8 bits, MSB shifts first
5kHz min, 40kHz max
6
6
response byte
command byte
>13us, <100us
>12us, <100us
>12us, <100us
5
5
4
4
3
3
2
2
1
1
0
0
Figure 3-1 SPI Timing Diagram
output floats
before DRDY
goes low
<35us
data hold >=12us
after last clock
low-power sleep
3-state
3-state if left to float
sleep until automatic wake (~3s)
6
The host can shift data to and from the QT on the same cycle
(with overlapping commands). Due to the nature of SPI, the
return data from a command or request is always one SPI
cycle behind.
An acquisition burst always happens about 920µs after /SS
goes high after coming out of Sleep mode . SPI clocking
lasting more than 15ms can cause the chip to self-reset.
3.2.1 /SS Line
/SS acts as a framing signal for SPI data clocking under host
control. See Figure 3-1.
After a shift operation /SS must be pulsed high before being
pulsed low for 1-5 µs. This must be a minimum of 35µs after
the last clock edge on CLK. The device automatically goes
into sleep state during this interval, and wakes again after /SS
rises. If /SS is simply held low after a shift operation, the
device will remain in sleep state up to the maximum time
shown in Figure 3-1. When /SS is pulsed, another acquisition
burst is triggered.
If /SS is held high all the time, the device will burst in a
free-running mode at a ~17Hz rate. In this mode a valid
position result can be obtained quickly on demand, and/or
one of the two OUT pins can be used to wake the host. This
rate depends on the burst length which in turn depends on
the value of each Cs and load capacitance Cx. Smaller
values of Cs or higher values of Cx will make this rate faster.
Dummy /SS Burst Triggers: In order to force a single burst,
a dummy ‘command’ can be sent to the device by pulsing /SS
low for 10µs to 10ms; this will trigger a burst after the rising
edge of /SS without requiring an actual SPI transmission. In
order to ensure the sampling capacitors have enough time to
discharge after a short /SS pulse, DRDY is held high for
approximately 700µs before the burst occurring.
After the burst completes, DRDY will rise again to indicate
that the host can get the results.
~31ms
awake
400us typ
<1ms
QT511-ISSG R6.01/1005
sleep
~31ms
wake up on /SS line
>20us
<1ms
>1us, <5us