qt1060 Quantum Research Group, qt1060 Datasheet

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... Power: – 1.8V to 5.5V • Package: – 28-pin MLF RoHS compliant IC • Signal Processing: – Self-calibration – auto drift compensation – noise filtering – Adjacent Key Suppression™ • Applications: – Mobile appliances ™ QTouch 6-channel Sensor IC AT42QT1060 9505D–AT42–12/08 ...

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... AT42QT1060 SNS1K 2 SNS2K 3 VDD QT1060 4 VSS 5 IO5 IO6 6 SNS3K Pin Listing Name Type Description SNS1K capacitor and to key SNS2K capacitor and to key VDD P Positive power pin ...

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... SNS0K capacitor and to key I Input only O Output only, push-pull OD Open drain output AT42QT1060 If Unused, Connect To... Leave open and set as output Leave open and set as output Leave open and set as output Leave open Resistor to Vdd or Vss only in standalone mode Resistor to Vdd or ...

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... IO3 SNS2K 21 IO2 SNS2 20 IO1 SNS1K 19 IO0 SNS1 SNS0K SNS0 QT1060 VDD Rchg 100k SDA 22 SCL CHG some systems it may be desirable to connect RST to the master reset signal. check the following sections for component values capacitors (Cs0 – Cs5) 9: Series resistors (Rs0 – Rs5) ...

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... The QT1060 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress RF emissions. 2.2 Keys The QT1060 can have a minimum of two keys and a maximum of six keys. These can be constructed in different shapes and sizes. See dimensions. Unused keys should be disabled by removing the corresponding Cs and Rs components and connecting the SNS pins as shown in the “ ...

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... During calibration and during the detect integrator (DI) period, the LP mode is temporarily set to LP mode 1 for a faster response. The QT1060 operation is based on a fixed cycle time of approximately 16 ms. The LP mode setting indicates how many of these periods exist per measurement cycle. For example mode = 1, there is an acquisition every cycle (16 ms) ...

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... CHG line. The CHG line is open-drain and should be connected via a 100k resistor to Vdd necessary for minimum power operation as it ensures that the QT1060 can sleep for as long as possible. Communications wake up the QT1060 from sleep causing a higher power consumption if the part is randomly polled ...

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... Detect Threshold The device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see key-by-key basis using the key threshold I AT42QT1060 8 Section 2.11.3). 14). In addition, the guard channel needs to be included within the AKS mask with the Guard Channel Example Section 5 ...

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... For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouch Touch Technology area of Atmel’s website, www.atmel.com. 9505D–AT42–12/08 AT42QT1060 Section 5.20 on page 20). The fast DI will not be Section 5.22 on page 20). The chosen Cs value should ™ ...

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... It is assumed that a larger bypass capacitor (like1 µF) is somewhere else in the power circuit; for example, near the regulator. To assist with transient regulator stability problems, the QT1060 waits 500 µs any time it wakes up from a sleep state (i.e. in SLEEP and LP modes) before acquiring, to allow Vdd to fully stabilize ...

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... C-compatible hardware and transfers with the chip may be corrupted. 2 C-compatible address of 0x12. This is not changeable. Host to Device S SLA+W A MemAddress Description of Write Data Bits Description Start condition Slave address plus write bit Acknowledge bit AT42QT1060 Figure 5 C-compatible read. After reading the two 2 C-compatible hardware if either Device to Host A Data ...

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... The device returns an ACK, followed by a data byte. 8. The host must return either an ACK or NACK the host returns an ACK, the device subsequently transmits the data byte from b. If the host returns a NACK, it should then terminate the transfer by issuing the AT42QT1060 12 Description of Write Data Bits Description ...

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... SDA to Vss and SCL to Vdd. See information. 9505D–AT42–12/08 2 C-compatible master and slave devices can only drive these lines low or 2 C-compatible specifications (1 µs maximum). 2 C-compatible communications are not required, then standalone mode AT42QT1060 and should be chosen so that the  Section 2.3 on page 5 for more 13 ...

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... PWM mask R/W 27 Detection mask R/W 28 Active level mask R/W 29 User output buffer R R/W 31 PWM level R/W 32 – 39 Reserved AT42QT1060 14 2 C-compatible serial interfaces. Bit 7 Bit 6 Bit 5 R Major Calibrating Res'd Key5 R Res'd Input 6 Input 5 Writing a nonzero value forces a calibration Writing a nonzero value forces a reset ...

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... MINOR VERSION NUMBER: this is the 8-bit minor firmware revision number (0x00). 5.5 Address 4: Detection Status Table 5-5. Address 4 CAL indicates that the QT1060 is currently calibrating. KEY0 – 5: bits indicate which keys are in detection, if any; touched keys report as 1, untouched or disabled keys report as 0. 9505D–AT42–12/08 R/W Bit 7 ...

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... Relative referencing compensates for fast signal drifts that are common to all keys. This mode is suitable if the keys are placed close to each other and have closely matched burst lengths (see Section 2.11.3 on page the relative referencing drift rate. Default: 1 (relative referencing Off) AT42QT1060 16 Input Port Status b7 b6 ...

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... Longer intervals between measurements yield lower power consumption at the expense of slower response to touch. 9505D–AT42–12/08 Positive Recalibration Delay POSITIVE RECALIBRATION DELAY NTHR Keys 0 – MSB LP Mode MSB AT42QT1060 LSB LSB 17 ...

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... KEY0 – 5 (Key Mask): these bits control whether a change in the corresponding bit in the detection status register generates a transition on the CHG line. A cause a CHG request stops the corresponding bit from causing a CHG request. Default: 0xBF (all bits create a CHG request) AT42QT1060 18 Mode SLEEP ...

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... Section 5.24 on page 21 for I/O register precedence and example usage. Active Level Mask Reserved IO6 IO5 means the output generates an active high output means that the 1 Section 5.24 for IO register precedence and example usage. AT42QT1060 KEY4 KEY3 KEY2 KEY1 ...

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... KEY SIGNAL: addresses 40 – 51 allow key signals to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit key signals which are accessed as two 8-bit bytes, stored LSB first. These addresses are read-only. AT42QT1060 20 User Output Buffer ...

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... AT42QT1060 User Reg QTouch Key (bit n) (channel Untouched X Touched X Untouched X Touched ...

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... Detection Integrator ] Tune the sensitivity of the keys by adjusting the value of the sampling capacitor, Cs and the negative threshold (NTHR) [Address 16 – 21: NTHR] AT42QT1060 22 To Set Up I/O Lines Determine the direction of the I /O lines. If any lines are unused , set them to be outputs and leave them unconnected ...

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... Volts o - + +125 +1.8V to 5.5V ± Minimum Typical Maximum – – 0.2Vdd 0.6Vdd – – – – 0.5 Vdd - 0.7V – – – – ±1 – 8 – AT42QT1060 Units Notes sink source µA bits 23 ...

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... AC Specifications Parameter Description T Response time R F Sample frequency QT Power-up delay operate/calibration time C-compatible clock rate I2C Reset pulse width AT42QT1060 24 Idd (µA) at Vdd = 5V 3.3V 2.48 1.8 1745 1135 1615 1065 1545 1030 1510 1010 1500 1000 1485 995 1475 992 ...

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... E 0. TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 mm Exposed Pad, Micro Lead Frame Package (MLF) AT42QT1060 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 0 ...

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... Moisture Sensitivity Level (MSL) AT42QT1060 LTCODE 1060 1060 -MMU AT 28 Pin AT42 QT1060 -MMU Chip LTCODE Traceability Code Description 28-pin MLF RoHS compliant IC MSL Rating Peak Body Temperature MSL3 Chip Traceability Code Program week code number 1-52 where ...

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... Revision A – September 2008 Revision B – October 2008 Revision C – November 2008 Revision D – December 2008 9505D–AT42–12/08 History  Initial Release for code revision 3.0  Minor amendments to burst length limitations  Minor amendments to improve clarity  Chip ID updated AT42QT1060 27 ...

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