cs7410 Cirrus Logic, Inc., cs7410 Datasheet
cs7410
Related parts for cs7410
cs7410 Summary of contents
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... CD-based digital audio market. With a powerful RISC processor, one DSP, integrated audio ∆Σ modulator, large internal SRAM and program ROM, and glueless in- terface to popular CD chip sets, the CS7410 is a complete single chip low-power programmable audio de- coder. This powerful architecture is easily capable of MP3, WMA, AAC CS7410’ ...
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... SDRAM Interface ................................................................................ 6 1.1.4.2 Serial Interface .................................................................................... 9 1.1.4.3 EDO DRAM Interface ........................................................................ 10 1.1.4.4 FLASH / ROM Interface .................................................................... 12 1.1.4.5 Audio Output Interface ...................................................................... 14 1.1.4.6 CD Interface ...................................................................................... 15 1.1.4.7 Miscellaneous Timings ...................................................................... 17 2. CS7410 SUMMARY ............................................................................................................... 18 2.1 CS7410 Typical Application ........................................................................................... 18 2.2 CS7410 Block Summaries ............................................................................................. 18 2.2.1 RISC-32 ............................................................................................................ 18 2.2.2 DSP-16 .............................................................................................................. 18 2.2.3 System Controls ................................................................................................ 19 2.2.4 Memory System ................................................................................................ 19 2.2.5 CD Interface ...................................................................................................... 19 2.2.6 Audio Interface .................................................................................................. 19 2.2.7 External Interface .............................................................................................. 19 2.2.8 System Functions .............................................................................................. 19 3. FUNCTIONAL DESCRIPTION .............................................................................................. 20 3 ...
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... Figure 11. FLASH/ROM Write....................................................................................................... 13 Figure 12. Audio Output Timing .................................................................................................... 14 Figure 13. CD Interface Timing ..................................................................................................... 15 Figure 14. CD Interface Timing Diagrams..................................................................................... 16 Figure 15. Miscellaneous Timings................................................................................................. 17 Figure 16. CS7410 Application ..................................................................................................... 18 Figure 17. CS7410 Pin Identification............................................................................................. 22 Figure 18. 100-Pin LQFP Package ( 1.4 mm) ............................................................... 34 LIST OF TABLES Table 1. SDRAM Characterization Data ......................................................................................... 6 Table 2. Serial Interface Characterization Data .............................................................................. 9 Table 3 ...
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... AMB P Power consumption TOT CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next table. 1.1.2 RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage, IO Supply Voltage, core and PLL ...
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... I Normal Operating, Playing MP3 Disc buffer rating buffer rating OUT SS DD CS7410 o C for the industrial part (-I part number)) Min Typ Max Units - Volts Volts µ ...
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... M_D[15:0] hold time after DR_CKO mhr a.Guaranteed by Design DR_CKO M_WE_L M_A DR_RAS_L DR_CAS_L M_D (write) t msur M_D (read) 6 Description Table 1. SDRAM Characterization Data t mper t mco t mdow t mhr Figure 1. SDRAM Timing CS7410 Min Typ Max Unit ...
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... DR_CKO DR_RAS_L DR_CAS_L M_A M_D M_WE_L DR_CKO DR_RAS_L DR_CAS_L ADRAS M_A M_D M_WE_L DS553PP3 Figure 2. SDRAM Load Mode ADCAS D0 D1 ... Figure 3. SDRAM Burst Write CS7410 Dn 7 ...
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... DR_CKO DR_RAS_L DR_CAS_L ADRAS M_A M_D M_WE_L DR_CKO DR_RAS_L DR_CAS_L M_A M_D M_WE_L 8 ADCAS D1 D2 Figure 4. SDRAM Burst Read Figure 5. SDRAM Refresh CS7410 ... Dn DS553PP3 ...
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... Design SER2_CLK (CPOL=0) t CMs SER2_CLK (CPOL=1) t DMs SER2_DO MSB (master) t DSs SER2_DI MSB (slave) SER2_CS DS553PP3 Description Table 2. Serial Interface Characterization Data t clk_per t DMh t DSh Figure 6. Serial Interface Timing Diagram CS7410 Min Typ Max Unit ...
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... ROE t RAS rise to OE rise OER t Read data hold to CAS rise DCH Note: Values shown are for minimum internal clock period (11 ns) and all programmed wait states enabled. 10 Description Table 3. EDO DRAM Characterization Data CS7410 Min Typ Max Unit ...
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... WDS DATA t RAS t RCL t CAS t CPN t t RAH ASC ADCAS t AA DATA Figure 8. EDO Page Read Timing Diagram t RAS t CHR Figure 9. EDO Refresh Timing Diagram CS7410 CRH t CAH ADCAS t WDH DATA OER CRH t CAH ADCAS t t CAC DCH ...
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... Note: Values shown are for minimum internal clock period (11 ns) and no programmed wait states. NVM_CE_L M_WE_L M_AP_OE M_A M_D 12 Description a Table 4. FLASH/ROM Read Characterization Data t CSpw t RDd1 t ADs t DAS Figure 10. FLASH/ROM Read CS7410 Min Typ Max Unit 135 - - -10 - ...
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... NVM_CE_L M_A M_D t M_WE_L WRSU M_AP_OE DS553PP3 t WRPW Figure 11. FLASH/ROM Write CS7410 t WRH 13 ...
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... Table 5. Audio Output Interface Symbols and Characterization Data a.Guaranteed by Design b.Active clock edge is programmable. Timing is referenced from the active edge. PCM_XCK(Input/Output) PCM_BCK(Output) PCM_BCK(Output) PCM_LRCK(Output) PCM_DO[1:0] (Output) 14 Description axch t t lrds t adsm Figure 12. Audio Output Timing CS7410 Min Typ Max 440 - - - - ...
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... CD_DATA and CD_C2P0 setup to CD_BCK active edge sdi t CD_DATA and CD_C2P0 hold time after CD_BCK active edge hsdi Note: Active edge of CD_BCLK is programmable CD_BCK(Input)* CD_LRCK(Input) CD_DO (Input) CD_C2PO (Input) DS553PP3 Description t slri t sdi Figure 13. CD Interface Timing CS7410 Min Typ Max Units hsdi ns ...
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... LSB MSB 1 0 Invalid Left Channel LSB MSB Upper (Right Channel) Lower (Left Channel) Upper (Left Channel) CS7410 LSB 1 0 LSB LSB MSB ...
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... XTLCLK period xclper t RST_N Low Pulse Width rstl t GPIO PW High gph GPIO PW Low t gpl a.Value represents typical application with 16.934 MHz crystal XTLCLOCK DS553PP3 Description RESET-N t gph GPIO Figure 15. Miscellaneous Timings CS7410 Min Typ Max - 59.05 - 1000 - - xccper rst ...
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... CS7410 SUMMARY 2.1 CS7410 Typical Application Figure 16 shows an example of a complete audio player using the CS7410. Debug ROM/FLASH (optional) 0-2 MB For new code 2.2 CS7410 Block Summaries 2.2.1 RISC-32 • Powerful 32-bit RISC processor • Comprehensive development tool support • Big or little endian data formats supported • ...
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... Includes clock divider and clock shutoff circuits for low power/sleep modes • Advanced 0.18 micron CMOS technology, runs off 1.8 V and 3.3 V • All I/O pins are 3.3 V, with 5 V tolerance • 100-pin LQFP package • Lead-free/industrial temperature range parts available DS553PP3 2 S connectivity bits CS7410 19 ...
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... C3 error decoding is done in software. The CD interface is compatible with all commonly used CD formats. The CS7410 contains a hardware pattern matching circuit to scan the incoming CD data for a pattern bytes. This circuit is used to assist the Electronic Shock Protection function by quickly locating and matching the incoming data with data stored in the ESP RAM. ...
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... The modulator has a 32x upsampling filter, followed by a 32x interpolator, and finally a 5 the modulator output, and there are separate programmable attenuators for the modulator output and both PCM outputs. DS553PP3 th -order Sigma-Delta modulator. The auto-mute circuit also works on CS7410 21 ...
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... PIN DESCRIPTION 4.1 Pin Identification Figure 17 shows the CS7410 pins grouped by function, also showing the number of pins in each group. CD Interface CD_BCLK CD_LRCK (4 pins) CD_DATA CD_C2P0 XTLCLK_I Misc. XTLCLK_O RST_N (8 pins) SER1_CLK SER1_DAT SER2_CLK SER2_CS Serial I/O SER2_DO (11 pins) SER2_DI SER3_CLK SER3_DO SER3_DO SER3_DO ...
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... Table 7 lists the pin number, pin name, and pin type for the 100-pin CS7410 package. For signal pins, the pin direction after reset is shown. The primary function and pin direction is shown for all signal pins. For some signal pins, a secondary function and direction are also shown. ...
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... GPIO[20 GPIO[21 GPIO[22 GPIO[23 GPIO[24 GPIO[25 GPIO[26 GPIO[27] B Table 7. Pin Assignments (Continued) CS7410 Function #2 Dir NVMem Address[7] O NVMem Address[6] O NVMem Address[5] O NVMem Address[4] O NVMem Address[3] O NVMem Address[2] O NVMem Address[1] O NVMem Address[ ...
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... I/O Power I Serial3 Chip Select1 I Servo Clock In I PCM_XCK I PCM_MUTE I CD_C2P0 I CD_BCLK I I CD_LRCK I I CD_DATA ∆Σ DAC Left P O ositive Out ∆Σ DAC Left O Negative Out - I/O Ground Table 7. Pin Assignments (Continued) CS7410 Dir Function #2 Dir GPIO[7] B ...
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... The main system clock can be derived from an external crystal connected between the XTLCLK_I and XTLCLK_O pins, or can be received from the CD servo chip via the XTLCLK_I pin. The CS7410 can accommodate a variety of input frequencies, such as 44.1 KHz x 256, x 384 512. Pin ...
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... SER3_SS1 4.4 SDRAM / DRAM Interface These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths bits are supported. The CS7410 supports word or block transfers (partial word transfers are not re- quired). Table 10 gives instructions on how to interface to any particular configuration of SDRAM. ...
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... Memory Auto Pre-charge. Always connect to RAM AP pin. Table 10. SDRAM Interface (Continued) Signal Name Type B Memory Data Bus. O Memory Address Bus. O Memory Row Address Strobe O Memory Column Address Strobe O Memory Write Enable O Memory Output Enable Table 11. EDO DRAM Interface CS7410 Description Description DS553PP3 ...
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... O Memory Address Bus[19..12] (shared with bits [15..8] of DRAM data bus). O Memory Address Bus[20] (DRAM BS_L pin). O NVRAM Write Enable (shared with DRAM WE_L pin) O NVRAM Write Enable (shared with DRAM WE_L pin) O ROM/NVRAM Chip Enable. Table 12. ROM/NVRAM Interface CS7410 Description 29 ...
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... PCM DAC. The sample rate and the size of the samples are programmable to accommo- date any commercially available DAC. The CS7410 has two data output pins, for channels of PCM output, and a separate output pin to simultaneously output IEC-958 encoded data (either compressed or uncompressed) ...
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... Pin Signal Name 81 CD_BCLK 82 CD_LRCK 83 CD_DATA 80 CD_C2P0 DS553PP3 Table 15. This interface is used to read serial CD data from a CD Type Description I CD clock input – polarity is programmable I CD left-right clock input I CD serial data input I CD error signaling input Table 15. CD Interface CS7410 31 ...
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... General Purpose Input/Output (GPIO) The CS7410 provides a number of General Purpose Input/Output (GPIO) pins, each with individual output three-state controls, and a number of General Purpose Output (GPO) pins. GPIO pins. A naming scheme for these pins was chosen to encourage system designers to adhere to stand- ardized pin usage. ...
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... Power and Ground Table 18 describes the power and ground pins. The CS7410 requires 3 different types of power supplies for the PLLs, internal logic, and IO pins. The PLLs and internal logic use 1.8 V supply voltage. The IO pins use 3.3 V supply voltage. An optional separate supply can be used to provide clean 3 the Sigma-Delta DACs digital output pads ...
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... The lead width with plating dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). 6) Ejector pin marks in molding are present on every package. 34 15.56 (0.613) 16.50 (0.650) 13.90 (0.547) 14.10 (0.555) Pin 1 Indicator 12.00 (0.472) REF 0.30 (0.012) 0.70 (0.028) Figure 18. 100-Pin LQFP Package ( 1.4 mm) CS7410 0.08 (0.003) 0.28 (0.011) 13.90 (0.547) 14.10 (0.555) 12.00 (0.472) REF 1.25 (0.049) 1.50 (0.059) 1.00 (0.039) REF 0° ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS553PP3 Table 19. Revision History Initial release Update AC specifications Add lead-free/industrial part number, delete MFQP packaging CS7410 Changes 35 ...