pi2eqx4401d Pericom Semiconductor Corporation, pi2eqx4401d Datasheet - Page 3

• Manufacturer Part Number: pi2eqx4401d
• Description: 2.5gbps X1 Lane Serial Pci-express Repeater/equalizer With Clock Buffer & Signal Detect Feature
• Manufacturer: Pericom Semiconductor Corporation

Pin Description
1, 6, 10, 23, 28
4, 9, 20, 25
06-0299
33, 34
13, 14
29, 30
17, 18
35, 36
Pin #
22
21
32
15
31
16
27
26
12
11
24
19
2
3
7
8
5
SIG_A, SIG_B
OUT+, OUT-
SEL[0:1]_A
SEL[0:1]_B
Pin Name
EN_[A,B]
SEL[2]_A
SEL[2]_B
SEL[3]_A
SEL[3]_B
CLKIN+
CLKIN-
AGND
AVDD
GND
IREF
AO+
BO+
V
AO-
BO-
AI+
BI+
AI-
BI-
DD
PWR
PWR
PWR
PWR
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
1.8V Supply Voltage
Positive CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
Negative CML Input Channel A with internal 50Ω pull down during normal
operation (EN_A=1). When EN_A=0, this pin is high-impedance.
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
Negative CML Input Channel B with internal 50Ω pull down during normal
operation (EN_B=1). When EN_B=0, this pin is high-impedance.
Selection pins for equalizer (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
Selection pins for amplifi er (see Amplifi er Confi guration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Confi guration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal
operation and 2KΩ pull up otherwise.
EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A
LVCMOS low selects a low power down mode.
Differential Input Reference Clock. If clock buffer is not used, then both
CLKIN+, CLKIN- should be pulled high to VDD.
Differential Reference Clock Output
1.8V Analog supply voltage
Analog ground
External 475Ω resistor connection to set the differential output current. If the
clock buffer is not used, then IREF should be unconnected (open).
SIG Detector output for channel A-B. Provides a LVCMOS high output when
an input signal greater than the threshold is detected
2.5Gbps x1 Lane Serial PCI-Express Repeater/Equalizer
3
with Clock Buffer & Signal Defect Feature
Description
PI2EQX4401D
PS8872F
11/17/06