pi2eqx5804nje Pericom Semiconductor Corporation, pi2eqx5804nje Datasheet - Page 9

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pi2eqx5804nje

Manufacturer Part Number
pi2eqx5804nje
Description
5.0gbps 4-lane Pcie Gen2 Redriver
Manufacturer
Pericom Semiconductor Corporation
Datasheet
Confi guration Register Summary
I2C Operation
The integrated I2C interface operates as a slave device, supporting standard rate operation of 100Kbps, with
7-bit addressing mode, with support for offset byte-write and read. The data byte format is 8 bit bytes. The
bytes must be accessed in sequential order from the lowest to the highest byte with the ability to stop after any
complete byte has been transferred. Address bits A4, A1 and A0 are programmable to support multiple chips
environment. The data is loaded until a Stop sequence is issued.
Note that the I2C inputs, SCL and SDA operate at 1.2V logic levels and are 3.3V tolerant.
Byte
0
1
2
3
4
5
6
7
8
9
10
11
07-0260
Mnemonic
SIG
RX50
LBEC
INDIS
OUTDIS
RESET
PWR
RXDE
AEOC
AEOC
RSVD
RSVD
Function
Signal Detect, indicates valid input signal level
Receiver Detect Output, indicates whether a receiver load was detected
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
Channel Input Disable, controls whether s channels input buffer is enabled or disabled
Channel Output Disable: Controls whether a channels output buffer is enabled or disabled
Channel Reset
Power Down Control, enables power down for each channel individually
Receiver Detect Enable, controls the receiver detect operation
A-Channels Equalizer and Output Control
B-Channels Equalizer and Output Control
Reserved
Reserved
9
5.0Gbps 4-Lane PCI Express Gen2 Re-Driver with
Equalization & Emphasis
PS8926A
PI2EQX5804
11/19/07

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