stled325 STMicroelectronics, stled325 Datasheet - Page 31

• Manufacturer Part Number: stled325
• Description: I?c Interfaced, Advanced Led Controller/driver With Keyscan, Standby Power Management And Real Time Clock Rtc
• Manufacturer: STMicroelectronics

STLED325
3.18
Note:
Bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage (typical voltage is 3.3 V) via a pull-up resistor (typical
value is 10 K). The following protocol has been defined.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain High.
Start data transfer: A change in the state of the data line, from high to Low, while the clock
is High, defines the START condition.
Stop data transfer: A change in the state of the data line, from Low to High, while the clock
is High, defines the STOP condition.
Data valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the high period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge: Each byte of eight bits is followed by one Acknowledge Bit. This
Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of each byte that has been clocked out of the
master transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Refer to Philips I
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is High.
- Changes in the data line, while the clock line is High, will be interpreted as control
signals.
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Functional description
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