pxb4330 Infineon Technologies Corporation, pxb4330 Datasheet - Page 112

• Manufacturer Part Number: pxb4330
• Description: Ics For Communications
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 21 MASK2/MASK3
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
MASK2(15:0)
MASK3(15:0)
Note: Registers MASK2 and MASK3 are only involved when accessing the Queue
Control Table (QCT). Due to the fact that only Read access is recommended for
this part of the QCT entries (see
QCT0..3), MASK2 and MASK3 should be programmed to FFFF
initialization and should not be changed during operation.
15
7
Table Access Mask Registers 2/3
14
Mask Register 2
Mask Register 3
Mask Registers 0..3 control the Read-Modify-Write access from the
respective transfer registers to the internal tables on a per-bit
selection basis. The Mask Registers correspond to the respective
transfer registers (LCI0/LCI1, TCT0/TCT1, QCT0..3, SOT0/SOT1):
0
1
6
Read/Write
0000
MASK2
Written by CPU to control internal table Read/Write
access
H
13
5
The dedicated bit of the transfer register is not
overwritten by the corresponding table entry bit during
Read; but overwrites the table entry bit during the
Modify-Write process.
This is a Write access to the internal table entry.
The dedicated bit of the transfer register is overwritten
by the corresponding table entry bit during Read and is
written back to the table entry bit during Modify-Write.
This is a Read access to the internal table entry.
3D
H
12
MASK(15:8)
Queue Configuration Table Transfer Registers
4
MASK(7:0)
6-112
MASK3
11
3
10
2
Register Descriptions
3E
H
9
1
PXB 4330
H
during
8
0
09.99