pxb4360f Infineon Technologies Corporation, pxb4360f Datasheet - Page 47

• Manufacturer Part Number: pxb4360f
• Description: Content Addressable Memory Element Came
• Manufacturer: Infineon Technologies Corporation

For single chip applications, the CAME device must be configured as master by CA and the
CI(1..0) inputs must be supplied with low level, pretending an “always mismatch” condition of the
non-existent slave. The CI(2) input is not evaluated by a chip configured as master, but it needs
connection to ground.
If two CAME chips are cascaded, the selection of which device will react and may respond is
made based on the command started. No additional preparation at the bus interface is
necessary. In read or write command cycles, the LCI - at least part of the command word -
Data Sheet
CA
CI(1..0)
CI(2)
CO(1..0) 00
CO(2)
0
0
1
00
01
10
11
1
01
10
11
0
1
CI(2) is ignored by a master.
Device is master, its LCI range is 0..8191
Device is slave, its LCI range is 8192..16383
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result mismatch on the opposite chip
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch on the opposite chip
No request is processed by the opposite chip
Request #4..6 is processed by the opposite chip
A slave interprets CI(2) as follows:
Data output at DAT is prohibited in read cycles
Data output at DAT is allowed in read cycles
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result mismatch
A search request (#1..3 or #4 with MODE.CEE= 1) is running
with the result of single match or multimatch
No request is processed
Request #4..6 is processed
CO(2) of a slave is undefined.A master outputs CO(2) as
follows:
Prohibit data output of a slave in read cycles
Allow data output of a slave in read cycles
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input
input
input
output
output
07.2000