pxb4219 Infineon Technologies Corporation, pxb4219 Datasheet - Page 155

• Manufacturer Part Number: pxb4219
• Description: Iwe8 Interworking Element For 8 E1/t1 Lines
• Manufacturer: Infineon Technologies Corporation

a_crv_en
a_dummy_
rts
a_emg_
bpslct
a_ovf_cnt_
en
a_ptr_prty
a_even_pck Even parity check for internal/external RAM and UTOPIA
Data Sheet
Clock recovery interface enable
0 =
1 =
Dummy RTS value
Dummy RTS value that will be transmitted in the first and second SRTS
period after start of segmentation.
Emergency byte-pattern select
00 =
01 =
10 =
11 =
Output queue overflow counter enable
0 =
1 =
SDT pointer even parity generation
0 =
1 =
0 =
1 =
Enabled
Disabled
Enabled
Byte-pattern 0, defined in bp10[bp0] selected
Byte-pattern 1, defined in bp10[bp1] selected
Byte-pattern 2, defined in bp32[bp2] selected
Byte-pattern 3, defined in bp32[bp3] selected
Disabled
Disabled: Fixed value in bit 7 of pointer field: “0”.
Enabled (recommended)
Odd parity check enabled (default operation)
The parity checkers expect the normal parity.
Even parity check enabled
The parity checkers expect the inverse parity. This mode tests
the proper operation of the parity generators/checkers.
155
PXB4219 / PXB4220 / PXB4221
Register Description
2002-05-06