ad9388a Analog Devices, Inc., ad9388a Datasheet
ad9388a
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ad9388a Summary of contents
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... HDCP processing and decryption are not required, the AD9388ABSTZ-5P derivative is available. This allows users who are not HDCP adopters to purchase the AD9388A. See the Ordering Guide for details on these derivative parts. Fabricated in an advanced CMOS process, the AD9388A is available in a space saving, 144-lead, surface-mount, RoHS- compliant, plastic LQFP and is specified over the − ...
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... Added Figure 6 ................................................................................ 13 Added Table 7 .................................................................................. 13 Changes to Component Processor Pixel Data Output Modes Section .............................................................................................. 16 Changes to Component Processor (CP) Section........................ 17 Added AD9388A/ADV7441A Evaluation Platform Section .... 24 Changes to Ordering Guide .......................................................... 25 10/07—Revsion Sp0: Initial Version Component Processor Pixel Data Output Modes .................. 16 Component Video Processing .................................................. 16 RGB Graphics Processing ......................................................... 16 General Features ...
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... FUNCTIONAL BLOCK DIAGRAM FORMATTER OUTPUT Figure 1. Rev Page AD9388A 06915-001 DDCB_SCL DDCB_SDA DDCA_SDA DDCA_SCL ...
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... AD9388A SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1. 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted. Table 1. 1 Parameter Symbol 2 STATIC PERFORMANCE Resolution (Each ADC) N Integral Nonlinearity INL Differential Nonlinearity ...
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... Graphics RGB sampling @ 108 MHz 6 6 YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz to T MIN MAX = 48 kHz and MCLKOUT = 256 Rev Page AD9388A Typ Max 105 95 118 174 278 180 284 ...
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... AD9388A ANALOG AND HDMI SPECIFICATIONS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1. 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted. Table Parameter ANALOG Clamp Circuitry External Clamp Capacitor Input Impedance (Except Pin 74) ...
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... T ). MIN MAX AD9388A Unit MHz ppm kHz MHz kHz μs μs μs μ μs kHz μs μs μs μ μ duty cycle duty cycle ...
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... AD9388A Timing Diagrams t 3 xDA xCL NOTES 1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S. LLC P0 TO P29, VS, HS, FIELD/ SCLK LRCLK t 16 I2Sx LEFT-JUSTIFIED MODE I2Sx MODE I2Sx RIGHT-JUSTIFIED MODE NOTES 1. THE SUFFIX x REFERS TO PIN NAMES ENDING WITH AND 3. ...
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... LQFP (ST-144) 1 Junction-to-package surface thermal resistance. PACKAGE THERMAL PERFORMANCE To reduce power consumption during AD9388A operation, turn off unused ADCs four-layer PCB that includes a solid ground plane, the θ value is 25.3°C/W. However, due to variations within the PCB metal and, therefore, variations in PCB heat conductivity, the value of θ ...
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... CVDD 111, 123, 127, 139 TVDD 73, 74, 91, 108 TEST0, TEST1, TEST3, TEST5 89 TEST2 107 TEST4 96, 98, 99 AIN1 to AIN12 AD9388A TOP VIEW (Not to Scale) Figure 5. Pin Configuration Type 1 Description G Digital Ground. G Analog Ground. G PLL Ground. ...
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... O This pin should be connected to the 28.63636 MHz crystal or left connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the AD9388A. In crystal mode, the crystal must be a fundamental crystal. I Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3 ...
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... External Clamp Signal. This is an optional mode of operation for the AD9388A. I Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the AD9388A. I Sets Internal Termination Resistance. Connect this pin to TGND using a 500 Ω resistor. Rev Page ...
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... TEST5, TEST3, 74, 73 TEST1, TEST0 Test 24 to Test16 76, 78, 80, 93, 94, 95, 96, 98 TEST2 107 TEST4 77, 79, 81 AIN1 to AIN3 AD9388ABSTZ-A5 TOP VIEW (Not to Scale) Figure 6. AD9388ABSTZ-A5 Derivative Pin Configuration 1 Type Description G Digital Ground. G Analog Ground. G PLL Ground. G Comparator Ground. G Terminator Ground. P Digital I/O Supply Voltage (3 ...
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... V 28.63636 MHz clock oscillator source is used to clock the AD9388A. In crystal mode, the crystal must be a fundamental crystal. I Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the AD9388A. O The recommended external loop filter must be connected to this ELPF pin. O The recommended external loop filter must be connected to AUDIO_ELPF ...
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... O Audio Serial Clock Output. O Audio Master Clock Output. I External Clamp Signal. This is an optional mode of operation for the AD9388A. I Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the AD9388A. I Sets Internal Termination Resistance. Connect this pin to TGND using a 500 Ω ...
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... AD9388A. More details are available in the Theory of Operation section. ANALOG FRONT END The analog front end of the AD9388A provides three high quality 10-bit ADCs to enable true 10-bit video decoding, a multiplexer with 12 analog input channels to enable a multisource connection without the requirement of an external multiplexer, and three current and voltage clamp control loops to ensure that dc offsets are removed from the video signal ...
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... CP include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The CP section of the AD9388A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness) ...
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... AD9388A PIXEL OUTPUT FORMATTING Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Component Processor Pixel Output Pin Map (P19 toP0) 1 Processor Mode/Format CP Mode 1 Video output 2 8-bit 4:2:2 CP Mode 2 Video output 2 10-bit 4:2:2 CP Mode 3 Video output 2 12-bit 4:2:2 CP Mode 4 ...
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... CrCb[1:0] – – CrCb[1:0] – CrCb[3:0] rCb[11:4] C CHC[7:0] (for example, B[7:0] or Cb[7:0]) CHB[7:0] (for example, R[7:0] or Cr[7:0]) Rev Page AD9388A CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0 – – ...
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... AD9388A 1 Processor Mode/Format 29 CP Mode 14 Video output 3, 4 24-bit 4:4:4 CP Mode 15 Video output 24-bit 4:4 Mode 16 Video output 30-bit 4:4 Mode 17 Video output 30-bit 4:4 Mode 18 Video output 30-bit 4:4 Mode 19 Video output 30-bit 4:2 processor uses digitizer or HDMI as input. 2 Maximum pixel clock rate of 54 MHz. ...
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... HDMI Map 0x68 Repeater/KSV Map 0x64 EDID Map 0x6C USER MAP SA: 0x40 SCL SDA 2 C-compatible) interface. The AD9388A has eight maps, each with a unique Address with ALSB = High Programmable Address 0x42 Not programmable 0x46 Programmable 0x62 Programmable 0x4A Programmable 0x4E ...
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... AD9388A TYPICAL CONNECTION DIAGRAM Figure 8. Typical Connection Diagram Rev Page ...
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... Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10. ELPF 70 10nF 1.69kΩ PVDD = 1.8V 82nF Figure 9. ELPF Components AUDIO_ELPF 102 Figure 10. AUDIO_ELPF Components Rev Page AD9388A 8nF 1.5kΩ PVDD = 1.8V 80nF ...
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... The front end of the platform consists of an EVAL- AD9388AFEZ_x or EVAL-ADV7441AFEZ_x board. This board feeds the digital outputs from the decoder to the FPGA on the motherboard. The EVAL-AD9388AFEZ_x or EVAL- ADV7441AFEZ_x board comes with one of the pin-compatible decoders shown in Table 11. On-Board Decoder ADV7441ABSTZ-170 ...
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... Front-end board for new evaluation platform; fitted with AD9388ABSTZ-170 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on the evaluation platform. 7 Front-end board for new evaluation platform; fitted with AD9388ABSTZ-5P decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on the evaluation platform. 8 Front-end board for new evaluation platform ...
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... AD9388A NOTES Rev Page ...
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... NOTES Rev Page AD9388A ...
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... AD9388A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06915-0-7/08(B) Rev Page ...