w83626f Winbond Electronics Corp America, w83626f Datasheet - Page 6

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w83626f

Manufacturer Part Number
w83626f
Description
Lpc To Isa Bridge Set
Manufacturer
Winbond Electronics Corp America
Datasheet
5.1.2
MEMCS16#
IOCHRDY
IOCHCK#
SA[19:17]
RSTDRV
IOCS16#
SYMBOL
SD[15:0]
SYSCLK
SA[16:0]
IOW#
IOR#
AEN
ISA Interface Signals
122-121
119-114
58-56
54-51
49-46
44-41
35-31
75-71
69-67
PIN
59
86
84
61
92
77
11
12
76
OUT 24
OUT 24
OUT 24
OUT 24
I/O24t
I/O 24t
I/O24t
I/O24t
I/O24t
I/O
IN t
IN t
IN t
System Address Bus. These are the upper address lines
that define the ISA’s byte granular address space (up to 1
M byte). SA [19:17] are at an unknown state upon
PCIRST#.
System Address Bus. These are the bi-directional lower
address lines that define the ISA’s byte granular address
space (up to 1 M byte). SA [16:0] is at an unknown state
upon PCIRST#.
System Data. SD [15:0] provides the 16-bit data path for
devices residing on the ISA Bus. W83626F/G tri-states SD
[15:0] during PCIRST#.
Address Enable. AEN is asserted during DMA cycles.
This signal is also driven high during W83626F/G initiated
refresh cycles. AEN is driven low upon PCIRST#.
I/O Read. IOR# is the command to an ISA I/O slave device
that the slave may drive data on to the ISA data bus (SD
[15:0]).
I/O Write. IOW# is the command to an ISA I/O slave device
that the slave may latch data from the ISA data bus (SD
[15:0]).
I/O Channel Ready. Resources on the ISA Bus negate
IOCHRDY to indicate that additional time (wait states) is
required to complete the cycle.
ISA bus. The SYSCLK is generated by dividing PCICLK by
3 or 4.
Reset Drive. W83628F asserts RSTDRV to reset devices
that reside on the ISA Bus. The W83628F asserts this
signal while the PCIRST# is asserted.
16-bit I/O Chip Select. This signal is driven by I/O devices
on the ISA Bus to indicate that they support 16-bit I/O bus
cycles.
Memory Chip Select 16. MEMCS16# asserted indicates
that the memory slave supports 16-bit accesses.
resource on the ISA bus during on detection of an error.
ISA System Clock. SYSCLK is the reference clock for the
I/O Channel Check. IOCHK# can be driven by any
W83626F/W83626D/W83626G
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FUNCTION

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