w83629d Winbond Electronics Corp America, w83629d Datasheet - Page 11

• Manufacturer Part Number: w83629d
• Description: Pci To Isa Bridge Set
• Manufacturer: Winbond Electronics Corp America

4.1.3
7.1.4 Power Signals
MEMR#
MEMW#
MASTER#
LA[23:17]
ROMCS#
REFRESH#
ZEROWS#
SMEMR#
SMEMW#
BALE
MEMCS16#
VCC
3VCC
GND
SYMBOL
SYMBOL
ISA Interface Signals, contiuned
127-
125
106
117
119
122
123
PIN
5-2
17
73
75
16, 38, 50, 65, 95,
6
7
1, 82, 102, 115
27, 46, 64
111, 128
OUT 24t
OUT 24t
OUT 24t
PIN
I/O 24t
I/O 24t
I/O 24t
I/O 24t
OD 24
I/O 12
I/O
IN t
IN t
Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write. MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER#. This signal is used with a DREQ line by an ISA
master to gain control of the ISA Bus.
Unlatched Address. The LA[23:17] address lines are bi-
directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
ROMCS# ,this pin weak pulled-down during PCIRST is
asserted, and apply a pull-up resistor (4.7 Kohm) to this pin
enable positive decoder of BIOS address range (depend on
Configure register 70 , bit 3,2). When BIOS assress range is
enabled , the PIN is BIOS ROM CS# output.
Refresh. REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83628F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate
that the current cycle can be executed as an ISA zero wait state
cycle. ZEROWS# has no effect during 16-bit I/O cycles.
Standard Memory Read. SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address
below 1 Mbyte.
Standard Memory Write. SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address
below 1 Mbyte.
Bus Address Latch Enable. BALE is an active high signal
asserted by the W83628F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
Memory Chip Select 16. MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
PWR
PWR
PWR
I/O
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5V Supply.
3.3V Supply.
Ground.
W83628F & W83629D
FUNCTION
Publication Release Date: May 18, 2005
FUNCTION
Revision A1