sak-xc2264m-72fxxl Infineon Technologies Corporation, sak-xc2264m-72fxxl Datasheet - Page 39

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sak-xc2264m-72fxxl

Manufacturer Part Number
sak-xc2264m-72fxxl
Description
16/32-bit Single-chip Microcontroller With 32-bit Performance
Manufacturer
Infineon Technologies Corporation
Datasheet
3
The architecture of the XC226xM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see
enabling the concurrent operation of several subsystems of the XC226xM.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC226xM.
Figure 3
Data Sheet
ADC1
10-Bit
Control, StandBy RAM
8-Bit
System Functions
Clock, Reset, Power
Flash Memory
Functional Description
PSRAM
Block Diagram
ADC0
10-Bit
8-Bit
Figure
BRGen
GPT
T2
T3
T4
T5
T6
3). This bus structure enhances overall system performance by
Analog and Digital General Purpose IO (GPIO) Ports
CC2
T7
T8
MPU
CCU6x
DPRAM
T12
T13
Interrupt Bus
..
..
MAC Unit
Interrupt & PEC
CCU60
XC2000 Family Derivatives / Base Line
CPU
T12
T13
39
XC2268M/67M, XC2265M/64M/63M
DSRAM
RS232,
USICx
IIC, IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
..
..
Functional Description
RS232,
USIC0
IIC , IIS
2 Ch.,
Buffer
64 x
LIN,
SPI,
MCHK
Debug Support
WDT
LXBus Control
RTC
MC_XY_BLOCKDIAGRAM
External Bus
Control
OCDS
EBC
Multi
CAN
V2.0, 2009-03

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