sak-xe164km-48fxxl Infineon Technologies Corporation, sak-xe164km-48fxxl Datasheet - Page 117

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sak-xe164km-48fxxl

Manufacturer Part Number
sak-xe164km-48fxxl
Description
16-bit Single-chip Real Time Signal Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
Table 35
Parameter
TCK clock period
TCK high time
TCK low time
TCK clock rise time
TCK clock fall time
TDI/TMS setup
to TCK rising edge
TDI/TMS hold
after TCK rising edge
TDO valid
after TCK falling edge
TDO high imped. to valid
from TCK falling edge
TDO valid to high imped.
from TCK falling edge
TDO hold after
TCK falling edge
1) The falling edge on TCK is used to generate the TDO timing.
2) The setup time for TDO is given implicitly by the TCK cycle time.
3) The setup time for TDO is given implicitly by the TCK cycle time.
Figure 26
Data Sheet
0.5
V
DDP
JTAG Interface Timing Parameters for Lower Voltage Range
Test Clock Timing (TCK)
1)
1)
2)3)
1)
t
2
Symbol
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
18
t
1
SR
SR
SR
SR
SR
SR
SR
CC
CC
CC
CC
t
3
XE164FM, XE164GM, XE164HM, XE164KM
Min.
50
16
16
6
6
5
117
XE166 Family Derivatives / Base Line
Values
Typ.
32
32
32
t
5
Max.
8
8
36
36
36
Unit Note /
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Electrical Parameters
t
4
Test Condition
MC_JTAG_TCK
V2.0, 2009-03
0.9
0.1
V
V
DDP
DDP

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