sak-c167cr-16rm ETC-unknow, sak-c167cr-16rm Datasheet - Page 57

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sak-c167cr-16rm

Manufacturer Part Number
sak-c167cr-16rm
Description
Microcomputer Components 16-bit Cmos Single-chip Microcontrollers
Manufacturer
ETC-unknow
Datasheet

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Parameter
ALE rising edge after RD,
WR
Address hold after RD,
WR
ALE falling edge to CS
CS low to Valid Data In
CS hold after RD, WR
ALE falling edge to RdCS,
WrCS (with RW-delay)
ALE falling edge to RdCS,
WrCS (no RW-delay)
RdCS to Valid Data In
(with RW-delay)
RdCS to Valid Data In
(no RW-delay)
RdCS, WrCS Low Time
(with RW-delay)
RdCS, WrCS Low Time
(no RW-delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
(with RW-delay)
Data float after RdCS
(no RW-delay)
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
RW-delay and
t
A
refer to the next following bus cycle.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
26
28
38
39
41
42
43
46
47
48
49
50
51
53
68
55
57
20Dec96@09:25h Intermediate Version
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
SR
SR
SR
SR
SR
SR
min.
-10 +
0 +
-5 -
10 +
20 +
-5 +
40 +
65 +
35 +
0
-10 +
10 +
Max. CPU Clock
t
t
F
t
A
t
t
t
t
t
t
A
t
F
A
C
C
C
t
F
= 20 MHz
F
F
55
max.
10 -
55
+
25 +
50 +
30 +
5 +
t
C
t
+ 2
t
F
t
t
t
A
C
C
F
t
A
min.
-10
+
0
+
-5 -
TCL - 15
+
TCL - 5
+
-5
+
2TCL - 10
+
3TCL - 10
+
2TCL - 15
+
0
-10
+
TCL - 15
+
t
t
t
t
t
t
t
t
t
t
1/2TCL = 1 to 20 MHz
F
F
F
A
A
C
C
C
F
F
Variable CPU Clock
t
A
Semiconductor Group
max.
10 -
3TCL - 20
+
2TCL - 25
+
3TCL - 25
+
2TCL - 20
+
TCL - 20
+
C167CR-16RM
t
t
t
t
t
C
C
C
F
F
+ 2
t
A
t
A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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