tc74act112 TOSHIBA Semiconductor CORPORATION, tc74act112 Datasheet
tc74act112
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tc74act112 Summary of contents
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... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT112P,TC74ACT112F,TC74ACT112FN Dual J-K Flip Flop with Preset and Clear The TC74ACT112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C MOS technology achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation ...
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... Don’t care System Diagram Outputs Function Clear H L Preset Change Toggle Change TC74ACT112P/F/FN 2007-10-01 ...
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... I IK ± ±50 I OUT ±100 500 (DIP) (Note 2)/180 (SOP) D −65 to 150 T stg Symbol Rating V 4 OUT CC − opr dt/ TC74ACT112P/F/FN Unit °C Unit °C ns/V 2007-10-01 ...
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... Other input GND ns Test Condition Symbol t W (L) ⎯ (H) ⎯ (L) ⎯ ⎯ ⎯ t rem 4 TC74ACT112P/F/ − 25°C 85°C Min Typ. Max Min Max ⎯ ⎯ ⎯ 2.0 2.0 ⎯ ⎯ ⎯ 0.8 0.8 ⎯ ⎯ 4.4 4.5 4.4 ⎯ ⎯ ⎯ ...
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... 500 Ω, input ns Test Condition V (V) Min CC ⎯ 5.0 ± 0.5 ⎯ 5.0 ± 0.5 ⎯ 5.0 ± 0.5 ⎯ ⎯ (per F/ TC74ACT112P/F/ − 25°C 85°C Typ. Max Min Max ⎯ 6.4 10.0 1.0 11.5 ⎯ 6.8 10.5 1.0 12.0 ⎯ ⎯ 85 100 85 ⎯ ⎯ ⎯ ...
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... Package Dimensions Weight: 1.00 g (typ.) TC74ACT112P/F/FN 6 2007-10-01 ...
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... Package Dimensions Weight: 0.18 g (typ.) TC74ACT112P/F/FN 7 2007-10-01 ...
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... Package Dimensions (Note) Note: This package is not available in Japan. Weight: 0.13 g (typ.) TC74ACT112P/F/FN 8 2007-10-01 ...
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... Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. TC74ACT112P/F/FN 9 20070701-EN GENERAL 2007-10-01 ...