EL5220C Elantec Semiconductor, Inc. (acquired by Intersil), EL5220C Datasheet - Page 12

• Manufacturer Part Number: EL5220C
• Description: Dual 12MHz Rail-to-Rail, I/o Op-amp
• Manufacturer: Elantec Semiconductor, Inc. (acquired by Intersil)

EL5220C, EL5420C
12MHz Rail-to-Rail Input-Output Op Amps
Unused Amplifiers
It is recommended that any unused amplifiers in a dual
and a quad package be configured as a unity gain fol-
lower. The inverting input should be directly connected
to the output and the non-inverting input tied to the
ground plane.
Driving Capacitive Loads
The EL5220C and EL5420C can drive a wide range of
capacitive loads. As load capacitance increases, how-
ever, the -3dB bandwidth of the device will decrease and
Figure 4. Package Power Dissipation vs
Figure 5. Package Power Dissipation vs
1200
1000
800
600
400
200
2.5
1.5
0.5
0
3
2
1
0
0
0
JEDEC JESD51-3 and SEMI G42-88 (Single Layer) Test
Board
JEDEC JESD51-7 High Effective Thermal Conductivity (4-
Layer) Test Board
(LPP exposed diepad soldered to PCB per JESD51-5)
833mW
667mW
606mW
485mW
2.500W
Ambient Temperature
Ambient Temperature
25
25
JA
JA
MSOP8
=120°C/W
=206°C/W
SO14
Ambient Temperature (°C)
Ambient Temperature (°C)
50
50
75
75
85
85
JA
=150°C/W
LPP16
JA
100
100
TSSOP14
MAX T
=165°C/W
J
=125°C
125
125
150
150
12
the peaking increase. The amplifiers drive 10pF loads in
parallel with 10k
100pF with 6.4dB of peaking. If less peaking is desired
in these applications, a small series resistor (usually
between 5
output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
“snubber” circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values
of 150 and 10nF are typical. The advantage of a snub-
ber is that it does not draw any DC load current or
reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5220C and EL5420C can provide gain at high
frequency. As with any high-frequency device, good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly rec-
ommended, lead lengths should be as short as possible
and the power supply pins must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, where the V
0.1µF ceramic capacitor should be placed from V
pin to V
be connected in parallel, placed in the region of the
amplifier. One 4.7µF capacitor may be used for multiple
devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are
to be used.
S
- pin. A 4.7µF tantalum capacitor should then
and 50 ) can be placed in series with the
with just 1.5dB of peaking, and
S
- pin is connected to ground, a
S
+ to