ssm2602 Analog Devices, Inc., ssm2602 Datasheet
ssm2602
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ssm2602 Summary of contents
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... MHz; and many common audio-sampling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 16 kHz, and 8 kHz. The SSM2602 can operate at power supplies as low as 1.8 V for the analog circuitry and 1.5 V for the digital circuitry. The maximum voltage supply is 3.6 V for all supplies. ...
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... SSM2602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Recommended Operating Conditions ...................................... 4 Digital Filter Characteristics ....................................................... 4 Timing Characteristics ................................................................ 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Converter Filter Response........................................................... 8 Digital De-Emphasis Characteristics ...
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... AVDD × AVDD/3.3 100 98 −80 − Rev. PrB | Page SSM2602 Unit Conditions μW V rms kΩ PGA gain = 0 dB kΩ PGA gain = +33 dB kΩ PGA gain = −34 PGA gain = 0 dB, AVDD = 3 PGA gain = 0 dB, AVDD = 1 ...
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... SSM2602 Parameter HEADPHONE OUTPUT Full-Scale Output Voltage Maximum Output Power Signal-to-Noise Ratio (A-Weighted) THD + N Power Supply Rejection Ratio Mute Attenuation LINE INPUT TO LINE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) Total Harmonic Distortion Power Supply Rejection MICROPHONE INPUT TO HEADPHONE OUTPUT ...
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... SCLK low pulse width ns SCLK high pulse width ns Hold time (start condition) ns Setup time (start condition) ns Data setup time 300 ns SDIN, SCLK rise time 300 ns SDIN, SCLK fall time ns Setup time (hold condition) 900 ns Data hold time Rev. PrB | Page SSM2602 ...
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... SSM2602 ABSOLUTE MAXIMUM RATINGS At 25°C, unless otherwise noted. Table 5. Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ...
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... Scale) INT/CLKOUT 6 16 LOUT BCLK 7 15 PGND Figure 2. Pin Configuration of SSM2602 Description Master Clock Input/Crystal Input Crystal Output Digital Core Supply Digital Ground Digital I/O Supply Buffered Clock Output Digital Audio Bit Clock. This pin is pulled down when the ACTIVE register is set to 0. ...
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... SSM2602 TYPICAL PERFORMANCE CHARACTERISTICS CONVERTER FILTER RESPONSE 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.5 1.0 1.5 f FREQUENCY ( S Figure 3. ADC Digital Filter Frequency Response 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 0 0.05 0.10 0.15 0.20 0.25 0.30 f FREQUENCY ( Figure 4. ADC Digital Filter Ripple 2.0 2.5 3.0 ) 0.35 0.40 0.45 0. Rev. PrB | Page Preliminary Technical Data 0 – ...
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... FREQUENCY ( ) Figure 10. De-Emphasis Error (44.1 kHz) 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 – kHz FREQUENCY ( ) Figure 11. De-Emphasis Frequency Response (48 kHz) 0.20 0.15 0.10 0. kHz FREQUENCY ( ) Figure 12. De-Emphasis Error (48 kHz) SSM2602 ...
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... SSM2602 THEORY OF OPERATION ADC HIGH-PASS FILTER DC offset can be removed by using the SSM2602 adjustable digital high-pass filter (see Table 3 for characteristics). Digital Filter Characteristics The ADC and DAC employ separate digital filters. AUTOMATIC LEVEL CONTROL (ALC) Codec has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level ...
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... Figure 15. Right-Justified Audio Interface LEFT CHANNEL Figure 16 Audio Interface Rev. PrB | Page Right justified Left justified mode Digital-signal processor (DSP) mode RIGHT CHANNEL RIGHT CHANNEL RIGHT CHANNEL SSM2602 1 N ...
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... SSM2602 ADCLRC/ DACLRC BCLK 1 2 ADCDAT/ DACDAT Figure 17. DSP/Pulse Code Modulation (PCM) Mode Audio Interface Submode 1 (SM1) [Bit LRP = 0] ADCLRC/ DACLRC BCLK 1 ADCDAT/ DACDAT Figure 18. DSP/PCM Mode Audio Interface Submode 2 (SM2) [Bit LRP = LEFT CHANNEL RIGHT CHANNEL ...
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... CSB Pin Setting 0 1 B12 B11 B10 B09 B08 B07 B06 B05 Figure 19. SPI Serial Interface 1 – – ADDR R/W ACK SUBADDRESS ACK 2 Figure 20. SSM2602 2-Wire I C Generalized Clocking Diagram B15 ... B9 B8 A(S) B7 ... B0 A(S) REGISTER REGISTER ADDRESS DATA B15 ... ... A1 ...
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... SSM2602 APPLICATIONS TBD Preliminary Technical Data Rev. PrB | Page ...
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... PROCESSOR MUX ADC RADCPD ATTEN ATTEN CLKOUTPD CLK GEN CLK GEN DIGITAL AUDIO INTERFACE CLKOUT DACDAT ADCDAT BCLK DACLRC ADCLRC Figure 22. SSM2602 Power Management Functional Location Diagram Rev. PrB | Page HPVDD HPVSS SSM2602 PWRPD REF DACPD RHPOUT DAC LHPPD ROUT ...
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... SDIN 27 SDIN SCLK 28 SCLK C6 0.1uF 1 MCLK/XTI Y1 2 POR/XTO 12.288MHz C7 C8 22pF 22pF Connection under chip Figure 23. SSM2602 Typical Application Circuit Rev. PrB | Page Preliminary Technical Data + C25 10uF C12 R11 1uF 100 R12 C13 100 C14 1uF R9 R10 47K 47K ...
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... HPOR PWROFF CLKOUTPD OSCPD OUTPD BCLKINV MS LRSWAP LRP CLKODIV2 CLKDIV2 SR [3: RESET [8:0] MAXGAIN [2:0] DCY [3:0] NGTH [4:0] Rev. PrB | Page SSM2602 LINVOL [5:0] RINVOL [5:0] LHPVOL [6:0] RHPVOL [6:0] INSEL MUTEMIC MICBOOST 000001010 DACMU DEEMPH [1:0] ADCHPD DACPD ADCPD MICPD LINEINPD 010011111 WL [1:0] FORMAT [1:0] BOSR ...
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... SSM2602 REGISTER MAP DETAILS LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00 Table 11. Left-Channel ADC Input Volume Register Bit Map D8 D7 LRINBOTH LINMUTE Table 12. Descriptions of Left-Channel ADC Input Volume Register Bits Bit Name Description LRINBOTH Left-channel line input volume update LINMUTE Left-channel input mute ...
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... Rev. PrB | Page SSM2602 RINVOL [5:0] ...
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... SSM2602 LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02 Table 15. Left-Channel DAC Volume Register Bit Map D8 D7 LRHPBOTH LZCEN Table 16. Descriptions of Left-Channel DAC Volume Register Bits Bit Name Description LRHPBOTH Right-channel headphone volume update LZCEN Left-channel zero cross detect enable LHPVOL [6:0] Left-channel headphone volume control RIGHT-CHANNEL DAC VOLUME, ADDRESS 0x03 Table 17 ...
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... DEEMPH [1:0] De-emphasis control ADCHPD ADC high-pass filter control SIDETONE_EN DACSEL BYPASS D4 D3 HPOR DACMU Rev. PrB | Page SSM2602 INSEL MUTEMIC MICBOOST Settings (default −6 dB (default − − − sidetone disable (default sidetone enable ...
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... SSM2602 POWER MANAGEMENT, ADDRESS 0x06 Table 23. Power Management Register Bit Map PWROFF CLKOUTPD Table 24. Bit Name Description PWROFF Whole chip power-down control CLKOUTPD Clock output power-down control OSCPD Crystal power-down control OUTPD Output power-down control DACPD DAC power-down control ...
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... MCLK divided by 2 See Table 30 and Table 31. USB mode 250 f (default 272 f S Normal mode 256 f (default 384 USB mode disable (default USB mode enable Rev. PrB | Page SSM2602 [1:0] FORMAT [1: format (default BOSR D0 D0 USB ...
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... SSM2602 Table 30. Sampling Rate Lookup Table, USB Disabled Sampling Rate Register Setting BOSR SR3 SR2 SR1 SR0 ...
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... Rev. PrB | Page ADC Sampling Rate (kHz) DAC Sampling Rate (kHz 88.2 88 Settings 0 = disable digital core (default activate digital core D2 D1 Settings 0 = reset (default ALCL [[3:0] SSM2602 D0 ACTIVE D0 D0 ...
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... SSM2602 ALC CONTROL 2, ADDRESS 0x11 Table 38. ALC Control 2 Register Bit Map Table 39. Descriptions of ALC Control 2 Register Bits Bit Name Description DCY [3:0] Decay (release) time control ATK [3:0] ALC attack time control NOISE GATE, ADDRESS 0x12 Table 40. Noise Gate Register Bit Map ...
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... Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev. PrB | Page 0.60 MAX PIN 1 INDICATOR 28 1 3.45 EXPOSED PAD 3. 0.25 MIN 3.00 REF Package Option CP-28-4 CP-28-4 CP-28-4 SSM2602 ...
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... SSM2602 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06858-0-9/07(PrB) Preliminary Technical Data Rev. PrB | Page ...