SC14046B
Phase Locked Loop
a voltage−controlled oscillator (VCO), source follower, and zener
diode. The comparators have two common signal inputs, PCA
PCB
signals, or indirectly coupled (with a series capacitor) to small voltage
signals. The self−bias circuit adjusts small voltage signals in the linear
region of the amplifier. Phase comparator 1 (an exclusive OR gate)
provides a digital error signal PC1
the center frequency between PCA
duty cycle). Phase comparator 2 (with leading edge sensing logic)
provides digital error signals, PC2
phase shift between PCA
immaterial). The linear VCO produces an output signal VCO
whose frequency is determined by the voltage of input VCO
capacitor and resistors connected to pins C1
source−follower output SF
the VCO
input Inh, when high, disables the VCO and source follower to
minimize standby power consumption. The zener diode can be used to
assist in power supply regulation.
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltage−to−frequency conversion and motor speed control.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
MAXIMUM RATINGS
August, 2008 − Rev. 0
Symbol
The SC14046B phase locked loop contains two phase comparators,
Applications include FM and FSK modulation and demodulation,
Phase Comparator 1 is an Exclusive OR Gate and is Duty Cycle Limited
Phase Comparator 2 Switches on Rising Edges and is not Duty Cycle
Limited
Buffered Outputs Compatible with MHTL and Low−Power TTL
Diode Protection on All Inputs
Supply Voltage Range = 3.0 to 18 V
Pin−for−Pin Replacement for CD4046B
Pb−Free Packages are Available*
Semiconductor Components Industries, LLC, 2008
V
T
Plastic “DW” Packages: – 7.0 mW/_C From 65_C To 125_C
V
P
T
I
stg
DD
in
in
in
D
A
. Input PCA
in
DC Supply Voltage Range
Input Voltage Range (All Inputs)
DC Input Current, per Pin
Power Dissipation, per Package
(Note 1)
Operating Temperature Range
Storage Temperature Range
signal is needed but no loading can be tolerated. The inhibit
in
Parameter
can be used directly coupled to large voltage
(Voltages Referenced to V
out
in
with an external resistor is used where
and PCB
out
in
out
, and maintains 90 phase shift at
and PCB
and LD, and maintains a 0
in
−0.5 to V
A
signals (duty cycle is
, C1
SS
−0.5 to +18.0
in
−55 to +125
−65 to +150
)
signals (both at 50%
Value
B
500
, R1, and R2. The
10
DD
+ 0.5
in
1
and the
in
Unit
mW
mA
V
V
C
C
and
out
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid ap-
plications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper op-
eration, V
V
logic voltage level (e.g., either V
puts must be left open.
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy
SS
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
This device contains protection circuitry to guard
Unused inputs must always be tied to an appropriate
v (V
in
in
ORDERING INFORMATION
and V
or V
A
WL
YY
WW
G
http://onsemi.com
out
out
) v V
DW SUFFIX
CASE 751G
should be constrained to the range
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
DD
Publication Order Number:
.
SS
16
or V
1
MARKING
DIAGRAM
DD
AWLYYWW
14046BG
SC14046B/D
). Unused out-