sc1470 Semtech Corporation, sc1470 Datasheet - Page 15

• Manufacturer Part Number: sc1470
• Description: Synchronous Buck Pseudo Fixed Frequency Power Supply Controller
• Manufacturer: Semtech Corporation

Layout Guidelines
VBAT = 8V to 20V
VOUT = 1.2V @ 6A
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground reference, VSSA, should be kept separate from power ground. All
components that are referenced to VSSA should connect to it locally at the chip. VSSA should connect to power
ground at the output capacitor(s) only.
The VOUT feedback trace must be kept far away from noise sources such as switching nodes, inductors and gate
drives. Route the feedback trace with VSSA as a differential pair from the output capacitor back to the chip. Run
them in a “quiet layer” if possible. VSSA may be separated from PGND using a zero Ohm resistor (that will be placed
at the bottom of the output capacitors) to aid in net separation.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins (VDDP and PGND, VCCA and VSSA) and
connected directly to them on the same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal, with the
current limit resistor located at the device.
We will examine the reference design used in the Design Procedure section while explaining the layout guidelines in
more detail.
POWER MANAGEMENT
PGOOD
2005 Semtech Corp.
VBAT
R1
1M
0402
C8
1nF
0402
C5
56p
0402
VOUT
R3
20k0
0402
R7
14k3
0402
R2
10R
0402
5VSUS
C10
1uF
0603
1
2
3
4
5
6
7
U1
EN/PSV
TON
VOUT
VCCA
FB
PGD
VSSA
Figure 4: Reference Design
N OTES
(1) R 6 is not required but aids k eeping VSSA s eparate f rom PGN D ex c ept where des ired in lay out.
SC1470
PGND
VDDP
ILIM
BST
DH
DL
LX
14
13
12
11
10
9
8
15
5VSUS
C9
1uF
0603
R4 7k87
0402
D1
SOD323
C1 0.1uF
0603
IRF7811AV
FDS6676S
Q1
Q2
VBAT
C2
2n2/50V
0402
L1
2u2
R6 0R (1)
C3
0u1/25V
0603
0402
C4
10u/25V
1210
+
C6
220u/25m
7343
www.semtech.com
SC1470
+
C7
220u/25m
7343
VOUT