peb4264 Infineon Technologies Corporation, peb4264 Datasheet
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S LIC - LIC - ...
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Edition 2006-10-10 Published by Infineon Technologies AG 81726 München, Germany Infineon Technologies AG 2006. © All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). ...
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SLIC-S / TSLIC-S Subscriber Line Interface Circuit Standard Feature Set Revision History: 2006-10-10, Revision 2.0 Previous Version: Revision 1.0 Page Subjects (major changes since last revision) Page 38 “Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package” on Page 38 Trademarks ...
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol SLIC-S/-S2 (PEF 4264/- ...
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List of Tables Table 1 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48- Table 2 Pin Definitions and ...
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General Description Infineon Technologies’ high voltage ringing Subscriber Line Interface Circuit SLIC-S (PEF 4264) Version 2.1 (V2.1) is the latest out of the well-known and broadly used SLIC-S family. It has been designed not only to cover all previous ...
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Subscriber Line Interface Circuit Standard Feature Set SLIC-S SLIC-S2 TSLIC-S Version 2.1 1.2 Features • High voltage SLIC with integrated ringing • Compatible with both 3.3 and 5 V systems • Available in single and dual-channel versions • High-voltage line ...
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Logic Symbol Tip/Ring interface Power supply Figure 1 Logic Symbol SLIC-S/-S2 (PEF 4264/-2) Tip/Ring interface channel A channel A Power supply channel A Tip/Ring interface channel B channel B Power supply channel B Figure 2 Logic Symbol TSLIC-S (PEF ...
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Pin Configuration Pin counting is clockwise! Figure 3 Pin Configuration PG-DSO-20-24 Package (top view) N.C. TIP N.C. BGND VHR VDD VBATL VBATH N.C. N.C. AGND N.C. Figure 4 Pin Configuration PG-VQFN-48-15 Package (top view) Preliminary Data Sheet IT 20 ...
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Figure 5 Pin Configuration PG-DSO-36-15 Package (dual channel) (top view) Preliminary Data Sheet RINGA 1 TIPA 2 BG NDA 3 VHRA 4 5 VDDA VBATLA 6 VBATH 7 AG NDA 8 TSLIC-S PEF 4364 9 CEXTA 10 RINGB PG-DSO-36-15 11 ...
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Pin Definitions and Functions Table 1 Pin Definitions and Functions PG-DSO-20-24 and PG-VQFN-48-15 Pin No. Pin No. Name PG-DSO- PG-VQFN- 20-24 48- RING 2 38 TIP 3 40 BGND 4 41 VHR 5 42 VDD 6 43 ...
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Table 2 Pin Definitions and Functions PG-DSO-36-15 Pin No. Name Pin Type 1 RINGA I/O 10 RINGB 2 TIPA I/O 11 TIPB 3 BGNDA GND 12 BGNDB 4 VHRA PWR 13 VHRB 5 VDDA PWR 14 VDDB 6 VBATLA PWR ...
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Functional Block Diagram AGND BGND VDD PDRH TIP RING PDRH V DOH VBATH VBATL Figure 6 Block Diagram Note the dual channel version both channels “A” and “B” are identical, channel ...
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Functional Description A functional block diagram is shown in SLIC-S V2.1 supports AC and DC control loops based on feeding a voltage I transversal line current and the longitudinal current Trans In receive direction, DC and AC voltages are ...
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Operating Modes SLIC-S V2.1 operates in the following modes controlled by ternary logic signals at C1 and C2: Table 3 SLIC-S Mode Table PDH M ACTL H HIRT 1) No ‘Overtemp’ signaling possible via pin ...
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High Impedance (HIR, HIT, HIRT) In these modes each of the line outputs can be programmed to show high impedance. HIT switches off the TIP buffer, while HIR switches off the RING buffer. The current through the active buffer is ...
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Typical Application Circuit for DuSLIC Figure 8 to Figure 9 show one channel of application circuits including SLIC-S / TSLIC-S V2.1 and SLICOFI ® VINETIC codec (please refer to the latest DuSLIC In Table 5 the recommended ...
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Figure 8 Application Circuit DuSLIC Preliminary Data Sheet Typical Application Circuit for DuSLIC® and VINETIC® ® 19 SLIC-S / TSLIC-S PEF 4264 / PEF 4364 Revision 2.0, 2006-10-10 ...
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Figure 9 Application Circuit VINETIC Preliminary Data Sheet Typical Application Circuit for DuSLIC® and VINETIC® ® 20 SLIC-S / TSLIC-S PEF 4264 / PEF 4364 Revision 2.0, 2006-10-10 ...
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Electrical Characteristics 4.1 Absolute Maximum Ratings Table 6 Absolute Maximum Ratings Parameter Battery voltage low Battery voltage high Battery voltage difference Auxiliary supply voltage Total battery supply voltage, continuous V supply voltage DD Ground voltage difference Input voltages Junction ...
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Table 8 Current Limits on Output Pins Current Duration Pins Continuous TIP, RING < TIP, RING < 100 s TIP, RING < TIP, RING The above limitations have to be regarded as typical. They are valid ...
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Electrical Parameters Unless otherwise stated, minimum and maximum values are valid within the full operating range. Testing is performed according to the specific test figures +3 Functionality and performance is guaranteed for T range ...
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Table 11 Supply Currents, Power Dissipation (I Parameter Symbol V I current BATL BATL V I current Current depending on supply voltage: 2) Current depending on supply voltage: 3) Current depending on line voltage: 4) Current depending ...
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DC Characteristics Table 13 DC Characteristics (V Parameter Symbol Line Termination TIP, RING V Differential DC line voltage TR Common mode DC line TIP voltage V DC line voltage drop – BATH V (see ...
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Table 13 DC Characteristics (V Parameter Symbol I IT output current normal IT polarity I IT output current reverse IT 4) polarity 1 G Transversal current ratio / 5) (see Figure 18) Off-hook output current on – ...
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Figure 10 Typical Buffer Voltage Drop in Operating Modes ACTL, ACTH, ACTR 4.5.3 AC Characteristics If not otherwise stated, AC characteristics are tested line current of ...
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Table 14 AC Characteristics (cont’d) Parameter Symbol LTRR-2 Longitudinal to transversal V V rejection ratio / (loop) long TR PEF 4264-2 (see Figure 19) TLRR Transversal to longitudinal V V rejection ratio / (see TR long Figure 21) PSRR Power ...
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Frequency Dependence of PSRR 0.1 Figure 11 Typical Frequency Dependence of PSRR 0.1 Figure 12 Typical Frequency Dependence of PSRR V Preliminary ...
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Figure 13 Typical Frequency Dependence of PSRR 0.1 Figure 14 Typical Frequency Dependence of PSRR V Preliminary Data Sheet PSRR V / ...
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Test Figures connected to BGND, VBATH (ACTH) BGND, VBATL (ACTL) VHR, VBATH (ACTR T,max R,max Figure 15 Output Current Limit R = ...
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Figure 17 Current Outputs IT TR,AC AC ...
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LTRR = long TR,AC LITRR = long IT 30 300 long ~ V TR, AC 300 Figure 19 Longitudinal to Transversal Rejection LTRR = loop ...
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TLRR = long 30 300 long V TR 300 Figure 21 Transversal to Longitudinal Rejection 450 V RNG 3 Figure 22 Ring Amplitude ...
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Package Outlines 6.1 PG-DSO-20-24 Package 1.1 -0.3 1.27 +0.13 0 45˚ Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side Figure 23 Package Outline for PG-DSO-20-24 (Plastic Green Dual Small Outline) ...
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PG-VQFN-48-15 Package Figure 24 Package Outline for PG-VQFN-48-15 (Plastic Green Very thin Profile Quad Flatpack No-lead) Note: Dimensions in mm Attention: The exposed die pad and the die pad edges are connected to VBATH via the chip substrate. Due ...
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PG-DSO-36-15 Package 1.1 ±0.1 0.65 +0.13 0.25 36 Index Marking 45˚ 1) Does not include plastic or metal protrusion of 0.15 max. per side Figure 25 Package Outline for PG-DSO-36-15 (Plastic Green Dual Small Outline) Notes ...
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Recommended PCB Foot Print Pattern for PG-DSO-36-15 Package The heatslug is soldered to the PCB according to another PCB metal layer as an additional cooling area is recommended. These copper areas should be both electrically separated from each other ...
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References [1] SLIC-S/-S2 / TSLIC-S (PEF 4264/-2 / PEF 4364) Application Note “Protection for SLIC-S/-S2 against Overvoltages and Overcurrents according to ITU-T K. 20/K.21/K.45” Rev. 1.0, 2003-07-18 ® [2] VINETIC Version 1.4 Prel. Application Note External Components Rev. 2.0, 2005-09-06 ...
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Published by Infineon Technologies AG ...