lt3475efe-trpbf Linear Technology Corporation, lt3475efe-trpbf Datasheet - Page 15

• Manufacturer Part Number: lt3475efe-trpbf
• Description: Dual Step-down 1.5a Led Driver
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LT3475 to maintain diode current regulation with PWM
pulse widths as short as 7.5 switching cycles (12.5μs for
f
the system and is unlikely to be longer than 12ms. Using
PWM periods shorter than 100μs is not recommended.
The maximum PWM dimming ratio (PWM
calculated from the maximum PWM period (t
minimum PWM pulse width (t
Total dimming ratio (DIM
dimming ratio and the current dimming ratio.
Example:
To achieve the maximum PWM dimming ratio, use the
circuit shown in Figure 9. This allows PWM pulse widths
as short as 4.5 switching cycles (7.5μs for f
Note that if you use the circuit in Figure 9, the rising edge
of the two PWM signals must align within 100ns.
SW
PWM1
t
I
t
I
PWM
DIM
MAX
MAX
MIN
RATIO
= 600kHz). Maximum PWM period is determined by
RATIO
/t
= 3.3μs (f
= 1A, I
RATIO
Figure 9. Extending the PWM Dimming Range
MIN
= 1A/0.1A =10:1
= PWM
= 10 • 3000 = 30000:1
220pF
= 9.9ms/3.3μs = 3000:1
MIN
1M
SW
= 0.1A, t
RATIO
= 1.4MHz)
R
T
R
RATIO
T
MAX
LT3475
GND
) is the product of the PWM
MIN
= 9.9ms
3475 F09
) as follows:
V
C
SW
3.3nF
RATIO
= 600kHz).
MAX
) can be
10k
0.1μF
) and
Layout Hints
As with all switching regulators, careful attention must
be paid to the PCB layout and component placement. To
maximize effi ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the SW
and BOOST pins have sharp rise and fall edges. Minimize
the area of all traces connected to the BOOST and SW
pins and always use a ground plane under the switching
regulator to minimize interplane coupling. In addition, the
ground connection for frequency setting resistor R
capacitors at V
should be tied directly to the GND pin and not shared
with the power ground path, ensuring a clean, noise-free
connection.
VIA TO LOCAL GND PLANE
Figure 10. Recommended Component Placement
C1
PWM1
, V
C2
pins (refer to the Block Diagram)
LT3475/LT3475-1
SHDN
V
IN
PWM2
15
3475 F10
T
and
3475fb