ncp4200 ON Semiconductor, ncp4200 Datasheet - Page 14

• Manufacturer Part Number: ncp4200
• Description: Programmable Multi-phase Synchronous Buck Converter With Pmbus
• Manufacturer: ON Semiconductor

following:
For a 150 A current limit R
TDC = 135 A then V
I
When I
This gives a value of 5 kW for R
changed the because the I
current limit and also the current out of the I
explained earlier.
I
at 900 mV full scale.
Active Impedance Control Mode
function of output current, the CSA gain and load−line
programming can be scaled to be equal to the droop
impedance of the regulator times the output current. This
droop voltage is then used to set the input control voltage to
the system. The droop voltage is subtracted from the DAC
reference input voltage directly to tell the error amplifier
where the output voltage should be. This allows enhanced
feed forward response.
Load Line Setting
NCP4200. It is programmed using the Load−line
Calibration (0xDE) and Load−line Set (0xDF) commands.
The load−line can be adjusted between 0% and 100% of the
external R
0.8 mW therefore programming the Load−line Calibration +
Load−line Set register to give a combined percentage of
80% will set the R
LOAD
MON
Table 4. Load−line Commands
From the Current Limit Set−point paragraph we know the
If the TDC and OCP limit for the processor have to be
The I
For controlling the dynamic output voltage droop as a
The load−line is programmable over the PMBus on the
voltage to 1.15 V MAX while maintaining accuracy
= 135 A.
0 0000
0 0001
1 0000
1 0001
1 1110
1 1111
LOAD
I
V
Code
MON
IMON
IMON
CSA
I
I
ILIMFS
IMON
pin also includes an active clamp to limit the
+ 10
= 135 A, I
+ 900 mV + 180 mA
. In this example R
+ 10
O
+
to 0.8 mW
1 mW
1 mW
Load−line (as a percentage of R
MON
MON
R
7.5 kW
LIMITFS
1 mW
LIMIFS
LIMFS
should equal 900 mV when
equals:
R
135 A
I
LOAD
LIMFS
51.6% = default
MON
CSA
= 7.5 kW. Assuming the
resistor sets up both the
I
3.226%
LOAD
53.3%
96.7%
100%
.
+ 180 mA
0%
= 1 mW R
R
MON
MON
O
needs to
(eq. 7)
(eq. 8)
pin, as
http://onsemi.com
CSA
)
14
Current Control Mode and Thermal Balance
each phase that are used for monitoring the per phase
current. This information is combined with an internal ramp
to create a current balancing feedback system that has been
optimized for initial current balance accuracy and dynamic
thermal balancing during operation. This current balance
information is independent of the average output current
information used for positioning. The magnitude of the
internal ramp can be set to optimize the transient response
of the system. It also monitors the supply voltage for
feed−forward control for changes in the supply. A resistor
connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp.
the PMBus Phase Bal SW(x) commands (0xE3 to 0xE6).
This allows each phase to be adjusted if there is a difference
in temperature due to layout and airflow considerations. The
phase balance can be adjusted from a default gain of 5 (Bits
4:0 = 10000). The minimum gain programmable is 3.75
(Bits 4:0 = 00000) and the max gain is 6.25 (Bits 4:0 =
11111).
Voltage Control Mode
amplifier is used for the voltage mode control loop. The
control input voltage to the positive input is set via the VID
logic according to the voltages listed in Table 10. The VID
code is set using the VID Input pins or it can be programmed
over the PMBus using the VOUT_Command. By default,
the NCP4200 outputs a voltage corresponding to the VID
Inputs. To output a voltage following the VOUT_Command
the user first needs to program the required VID Code. Then
the VID_EN Bits need to be enabled. The following is the
sequence:
The NCP4200 has individual inputs (SW1 to SW4) for
The balance between the phases can be programmed using
A high gain, high bandwidth, voltage mode error
1. Program the required VID Code to the
2. Set the VID_EN bit (Bit 3) in the VR Config 1 A
VOUT_Command code (0x21).
(0xD2) and on the VR Config 1B (0xD3).
This voltage is also offset by the droop voltage for
active positioning of the output voltage as a
function of current, commonly known as active
voltage positioning. The output of the amplifier is
the COMP pin, which sets the termination voltage
for the internal PWM ramps.
The negative input (FB) is tied to the output sense
location with Resistor R
and controlling the output voltage at this point. A
current source (equal to IREF) from the FB pin
flowing through R
offset voltage from the VID voltage. The no load
voltage is negative with respect to the VID DAC
for Intel CPU’s.
B
is used for setting the no load
B
and is used for sensing