ncp4201 ON Semiconductor, ncp4201 Datasheet - Page 29

• Manufacturer Part Number: ncp4201
• Description: Ncp4201 Programmable Multi-phase Synchronous Buck Converter With Pmbus
• Manufacturer: ON Semiconductor

Code
0xDA
0xDB
0xDC
0xDE
Cmd
0xD2
0xD3
0xD4
0xD5
0xD6
0xD8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Default
0x52
0x52
0x03
0x02
0x01
0x00
0x00
0x00
0x00
0x10
VR Config. 1A
VR Config. 1B
Ton Delay
Ton Rise
Ton Transition
EN/VTT Voltage
VMON Voltage
VOUT_TRIM
VOUT_CAL
Load−line Calibration
Description
http://onsemi.com
Bytes
#
1
1
1
1
1
2
1
1
1
1
29
6:4
Bit
This register is for security reasons. It has the same format as
register 0xD2. Bits need to be set in both registers for the function to
take effect.
This resister sets TD1, TD3 and TD5 delays for the soft−start
sequence. The current limit latchoff timer is 4 times the programmed
delay time:
000 = 0.5 ms
001 = 1 ms
010 = 1.5 ms
011 = 2 ms = default
100 = 2.5 ms
101 = 3 ms
110 = 3.5 ms
111 = 4 ms
This register sets the soft−start voltage slew rate, and hence TD2
and TD4, of the soft−start sequence:
000 = 0.1 V/ms
001 = 0.3 V/ms
010 = 0.5 V/ms = default
011 = 0.7 V/ms
100 = 0.9 V/ms
101 = 1.1 V/ms
110 = 1.3 V/ms
111 = 1.5 V/ms
This register sets the slew rate during dynamic VID.
This is a 16 bit value that reports back the voltage on the VTT Pin.
Voltage is reported using Linear Mode.
This is a 16 bit value that reports back the voltage measured
between FB and FBRTN. Voltage is reported using Linear Mode.
Offset Command Code for V
Offset Command Code for V
This value sets the internal load−line attenuation DAC calibration
value. The maximum load−line is controlled externally by setting the
gain of the current sense amplifier as explained in the applications
section. This maximum load−line can then be adjusted from 100% to
0% in 30 steps. Each LSB represents a 3.226% change in the
load−line.
00000 = No load−line
10000 = 51.6% of external load−line
11111 = 100% of external load−line
3
2
1
0
Enable Bits
LOOP_EN
CLIM_EN
VID_EN
Phase
Name
Res
000 = Phase 1
100 = Phase 2
010 = Phase 3
110 = Phase 4
When the VID_EN bit is set to 1, the VID
code in the VOUT_COMMAND register sets
the output voltage. When VID_EN is set to 0,
the output voltage follows the VID input pins.
When the LOOP_EN bit is set to 1 in both
registers, the control loop test function is
enabled. This allows measurement of the
control loop AC gain and phase response with
appropriate instrumentation. The control loop
signal insertion pin is I
output pin is COMP.
When CLIM_EN is set to 1, the current limit
time out latchoff functions normally. When this
bit is set to 0 in both registers, the current limit
latchoff is disabled. In this state, the part can
be in current limit indefinitely.
OUT
OUT
Comment
, max ±200 mV.
, max ±200 mV.
Description
MON
. The control loop