ada4320-1 Analog Devices, Inc., ada4320-1 Datasheet - Page 7

• Manufacturer Part Number: ada4320-1
• Description: High Power, Low Distortion Upstream Catv Line Driver Ada4320-1
• Manufacturer: Analog Devices, Inc.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 2, 8, 9, 12,
17, 18, 19,
EPAD
3, 4, 5
6
7
10
11
13
14
15
16
20, 22
21, 23
24
Mnemonic
GND
VCC
RAMP
TXEN
VIN−
VIN+
DATEN
SDATA
CLK
SLEEP
VOUT−
VOUT+
COMP
Description
Common External Ground Reference.
Common Positive External Supply Voltage.
External RAMP Capacitor (Optional).
Transmit Enable. Logic 0 disables forward transmission, and Logic 1 enables forward transmission.
Inverting Input. DC-biased to approximately V
Noninverting Input. DC-biased to approximately V
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition
transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer
into the register. A 1-to-0 transition inhibits the data latch (holds the previous, and simultaneously enables the
register for serial data load).
Serial Data Input. This digital input allows an 8-bit serial control word to be loaded into the internal register with the
most significant bit (MSB) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave shift register. A
Logic 0-to-1 transition latches the data bit, and a Logic 1-to-0 transition transfers the data bit to the slave. This
requires the input serial data-word to be valid at or before this clock transition.
Low Power Sleep Mode. In sleep mode, the supply current is reduced to 12 μA typical. Logic 0 powers down
the device, and Logic 1 powers up the device.
Negative Output Signal. This pin must be biased to V
Positive Output Signal. This pin must be biased to V
Internal Compensation. This pin must be externally decoupled (0.1 μF capacitor).
NOTES
1. EXPOSED THERMAL PAD MUST BE ELECTRICALLY AND
THERMALLY CONNECTED TO PCB GROUND (GND) PLANE.
RAMP
TXEN
GND
GND
VCC
VCC
VCC
Figure 4. Pin Configuration, Top View
1
2
3
4
5
6
7
ADA4320-1
Rev. 0 | Page 7 of 16
(Not to Scale
TOP VIEW
CC
/2. This pin should be ac-coupled with a 0.1 μF capacitor.
19
18
17
16
15
14
13
CC
GND
GND
GND
SLEEP
CLK
SDATA
DATEN
CC
/2. This pin should be ac-coupled with a 0.1 μF capacitor.
CC
.
.
ADA4320-1